Datasheet

Section 17 Serial Communication Interface 3 (SCI3)
Rev. 1.50 Sep. 18, 2007 Page 370 of 584
REJ09B0240-0150
Clock synchronous mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
Table 17.1 Channel Configuration
Channel Abbreviation Pin Register
Register
Address
Noise
Canceller
SMR H'FFFFA8
BRR H'FFFFA9
SCR3 H'FFFFAA
TDR H'FFFFAB
SSR H'FFFFAC
RDR H'FFFFAD
RSR 
Channel 1 SCI3*
2
SCK3
RXD
TXD
TSR 
None
SMR_2 H'FFF740
BRR_2 H'FFF741
SCR3_2 H'FFF742
TDR_2 H'FFF743
SSR_2 H'FFF744
RDR_2 H'FFF745
RSR_2 
Channel 2 SCI3_2 SCK3_2
RXD_2
TXD_2
TSR_2 
None
SMR_3 H'FFF600
BRR_3 H'FFF601
SCR3_3 H'FFF602
TDR_3 H'FFF603
SSR_3 H'FFF604
RDR_3 H'FFF605
RSR_3 
TSR_3 
Channel 3 SCI3_3 SCK3_3
RXD_3
TXD_3
SMCR_3*
1
H'FFF608
Yes