Datasheet

Section 17 Serial Communication Interface 3 (SCI3)
Rev. 1.50 Sep. 18, 2007 Page 371 of 584
REJ09B0240-0150
Note: 1. In addition to basic functions common in SCI3 and SCI3_2, SCI3_3 has the serial mode
control register (SMCR). SMCR controls noise canceling on the RXD_3 input signal,
PH2/TXD_3 pin function, and SCI3_3 module standby function.
2. The channel 1 of the SCI3 is used in on-board programming mode by boot mode.
• Serial mode control register (SMCR)
Bit Bit Name
Initial
Value R/W Description
7 to 3  All 1  Reserved
These bits are always read as 1.
2 NFEN_3 0 R/W Noise Cancel Function Select
When COM in SMR is cleared to 0 and this bit is set to 1,
noise in the RXD_3 input signal is taken.
1 TXD_3 0 R/W TXD_3 Pin Select
Selects PH2/TXD_3 pin function.
0: General input pin is selected
1: TXD_3 output pin is selected
0 MSTS3_3 0 R/W SCI3_3 Module Standby
When this bit is set to 1, SCI3_3 enters in the standby state.
• Noise canceller
The RXD_3 input signal is loaded internally via the noise canceller. The noise canceller
consists of three latch circuits and match detection circuit connected in series. The RXD_3
input signal is sampled on the basic clock with a frequency 16 times the transfer rate, and the
level is passed forward to the next circuit when outputs of three latches match. When the
outputs are not match, previous value is retained. In other word, when the same level is
retained more than three clocks, the input signal is acknowledged as a signal. When the level is
changed within three clocks, the change is acknowledged as not a signal change but noise.
RXD_3
input signal
Internal RXD_3 signal
in figure 17.1
Sampling clock
Sampling
clock
Internal basic clock
interval
C
Latch
Q
D
C
Latch
Q
D
C
Latch
Q
D
Match
detector
SCMR3
(NFEF_3)
Block Diagram of Noise Canceller