Datasheet

Section 17 Serial Communication Interface 3 (SCI3)
Rev. 1.50 Sep. 18, 2007 Page 372 of 584
REJ09B0240-0150
Clock
TXD
RXD
SCK3
TSR
RSR
TDR
SSR
SCR3
SMR
BRR
RDR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (φ/64, φ/16, φ/4, φ)
External
clock
BRC
Baud rate generator
Figure 17.1 Block Diagram of SCI3
17.2 Input/Output Pins
Table 17.2 shows the SCI3 pin configuration.
Table 17.2 Pin Configuration
Pin Name Abbreviation I/O Function
SCI3 clock SCK3 I/O SCI3 clock input/output
SCI3 receive data input RXD Input SCI3 receive data input
SCI3 transmit data output TXD Output SCI3 transmit data output