Datasheet

Section 17 Serial Communication Interface 3 (SCI3)
Rev. 1.50 Sep. 18, 2007 Page 375 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
2 MP 0 R/W Multiprocessor Mode
When this bit is set to 1, the multiprocessor communication
function is enabled. The PE bit and PM bit settings are invalid
in multiprocessor mode. In clock synchronous mode, clear this
bit to 0.
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits select the clock source for the baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting and
the baud rate, see section 17.3.8, Bit Rate Register (BRR). n
is the decimal representation of the value of n in BRR (see
section 17.3.8, Bit Rate Register (BRR)).
17.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, see section 17.7,
Interrupt Requests.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5 TE 0 R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.