Datasheet

Section 17 Serial Communication Interface 3 (SCI3)
Rev. 1.50 Sep. 18, 2007 Page 379 of 584
REJ09B0240-0150
17.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 17.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 17.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 17.3 and 17.4 are values in active (high-
speed) mode. Table 17.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clock synchronous mode. The values shown in table 17.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N =
φ
64 × 2
2n–1
× B
× 10
6
– 1
Error (%) = – 1 × 100






φ × 10
6
(N + 1) × B × 64 × 2
2n–1
[Clock Synchronous Mode]
N =
φ
8 × 2
2n–1
× B
× 10
6
– 1
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)