Datasheet

Section 18 I
2
C Bus Interface 2 (IIC2)
Rev. 1.50 Sep. 18, 2007 Page 432 of 584
REJ09B0240-0150
ICDRS
ICDRR
12345678 99
AA
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
User
processing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3] Set ACKBT
[3] Read ICDRR
[4] Read ICDRR
Data 2
Data 1
Figure 18.12 Slave Receive Mode Operation Timing (2)
18.4.6 Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1) Data Transfer Format
Figure 18.13 shows the clocked synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SDA
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SCL
Figure 18.13 Clocked Synchronous Serial Transfer Format