Datasheet

Section 19 A/D Converter
Rev. 1.50 Sep. 18, 2007 Page 449 of 584
REJ09B0240-0150
19.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name
Initial
Value R/W Description
7 TRGE 0 R/W Trigger Enable
A/D conversion is started by an assertion of the external
trigger signal from timer RD or the falling or rising edge
of the external ADTRG signal when this bit is set to 1.
The trigger source is selected by bits PMRG3 and
PMRG2 in port mode register G (PMRG).
The falling or rising edge of the external ADTRG signal
is selected by bits PMRG2 and PMRG1.
6 to 4 — All 1 — Reserved
These bits are always read as 1.
3, 2 — All 0 R/W Reserved
The write value should always be 0.
1 — 1 — Reserved
This bit is always read as 1.
0 CH3 0 R/W Reserved
Selects the analog input channel according to bits CH2
to CH0 in ADCSR.