Datasheet

Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional)
Rev. 1.50 Sep. 18, 2007 Page 466 of 584
REJ09B0240-0150
20.3.2 Low-Voltage Detection Circuit
(1) LVDR (Reset by Low Voltage Detect) Circuit
Figure 20.4 shows the timing of the LVDR function. The LVDR is enabled after a power-on reset
signal is negated.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR
clears the LVDRES signal to 0, and resets prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage (typ. = 3.6 V) again, prescaler S starts counting. It counts 131,072 clock (φ)
cycles, and then releases the internal reset signal. Since the LVDSEL bit in the LVDCR is
initialized to 1 at this point, Vreset during Vcc rising remains 3.6 V, even if the LVDSEL bit had
been set to 0.
Note that if the power supply voltage (Vcc) falls below V
LVDRmin
= 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
LVDRES
VCC
Vreset
VSS
V
LVDRmin
OVF
PSS-reset
signal
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 20.4 Operational Timing of LVDR Circuit