Datasheet

Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional)
Rev. 1.50 Sep. 18, 2007 Page 467 of 584
REJ09B0240-0150
(2) LVDI (Interrupt by Low Voltage Detection) Circuit
Figure 20.5 shows the timing of LVDI functions. To start the LVDI, set the LVDDE and LVDUE
bits in LVDCR to 1.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to the standby or subsleep
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
LVDINT
Vcc
Vint (D)
Vint (U)
VSS
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generatedIRQ0 interrupt generated
LVDDE
Vreset1
Figure 20.5 Operational Timing of LVDI Circuit