Datasheet

Section 22 List of Registers
Rev. 1.50 Sep. 18, 2007 Page 472 of 584
REJ09B0240-0150
22.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the specified basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses is prohibited. Correct operation of the access
itself or later operations is not guaranteed when such a register is accessed.
Register Name Abbreviation Bit No. Address
Module
Name
Data Bus
Width
Access
State
Timer RD counter_0 TRDCNT_0 16 H'FFF100 Timer RD
(Channel 0)
16*
1
4
General register A_0 GRA_0 16 H'FFF102 Timer RD
(Channel 0)
16*
1
4
General register B_0 GRB_0 16 H'FFF104 Timer RD
(Channel 0)
16*
1
4
General register C_0 GRC_0 16 H'FFF106 Timer RD
(Channel 0)
16*
1
4
General register D_0 GRD_0 16 H'FFF108 Timer RD
(Channel 0)
16*
1
4
Timer RD counter_1 TRDCNT_1 16 H'FFF10A Timer RD
(Channel 1)
16*
1
4
General register A_1 GRA_1 16 H'FFF10C Timer RD
(Channel 1)
16*
1
4
General register B_1 GRB_1 16 H'FFF10E Timer RD
(Channel 1)
16*
1
4
General register C_1 GRC_1 16 H'FFF110 Timer RD
(Channel 1)
16*
1
4
General register D_1 GRD_1 16 H'FFF112 Timer RD
(Channel 1)
16*
1
4
Timer RD counter_2 TRDCNT_2 16 H'FFF140 Timer RD
(Channel 2)
16*
1
4
General register A_2 GRA_2 16 H'FFF142 Timer RD
(Channel 2)
16*
1
4
General register B_2 GRB_2 16 H'FFF144 Timer RD
(Channel 2)
16*
1
4
General register C_2 GRC_2 16 H'FFF146 Timer RD
(Channel 2)
16*
1
4