Datasheet

Section 23 Electrical Characteristics
Rev. 1.50 Sep. 18, 2007 Page 511 of 584
REJ09B0240-0150
Values
Item Symbol Applicable Pins Test Condition
Min. Typ. Max.
Unit
Reference
Figure
On-chip oscillator
oscillation frequency
f
RC
Ta = -40°C to +85°C
FSEL = 0
VCLSEL = 0
30.40 32.00 33.60 MHz
Note: * Determined by the MA2, MA1, MA0, SA1, and SA0 bits in the system control register 2
(SYSCR2).
Table 23.4 I
2
C Bus Interface Timing
V
CC
= 3.0 to 5.5 V, V
SS
= 0.0 V, T
a
= –20 to +75°C/–40 to +85°C, unless otherwise indicated.
Values
Item Symbol
Test
Condition
Min. Typ. Max. Unit
Reference
Figure
SCL input cycle time t
SCL
12t
cyc
+ 600   ns Figure 23.4
SCL input high width t
SCLH
3t
cyc
+ 300   ns
SCL input low width t
SCLL
5t
cyc
+ 300   ns
SCL and SDA input fall
time
t
Sf
  300 ns
SCL and SDA input spike
pulse removal time
t
SP
  1t
cyc
ns
SDA input bus-free
time
t
BUF
5t
cyc
  ns
Start condition input hold
time
t
STAH
3t
cyc
  ns
Retransmission start
condition input setup time
t
STAS
3t
cyc
  ns
Setup time for stop
condition input
t
STOS
3t
cyc
  ns
Data-input setup time t
SDAS
1t
cyc
+20   ns
Data-input hold time t
SDAH
0   ns
Capacitive load of
SCL and SDA
c
b
0  400 pF
t
Sf
V
CC
= 4.0 to
5.5 V
  250 ns SCL and SDA output fall
time
  300