Datasheet

Rev. 1.50 Sep. 18, 2007 Page 573 of 584
REJ09B0240-0150
Main Revisions and Additions in this Edition
Item Page Revisions (See Manual for Details)
Section 5 Clock Pulse Generators
5.2.4 Clock Control/Status
Register (CKCSR)
76 Amended
Bit Bit Name Description
7
6
PMRJ1
PMRJ0
OSC Pin Function Select 1 and 0
PMRJ1 PMRJ0 OSC2 OSC1
0 0 I/O I/O
1 0 CLKOUT I/O
0 1 Hi-Z OSC1
(external clock input)
1 1 OSC2 OSC1
Section 14 Timer RD
Figure 14.54 Block Diagram of
Digital Filter
346 Amended
FTIOA0 (TCLK)
φ40M
φ/
32
φ/
8
φ/4
φ/2
φ
TPSC2 to
TPSC0
Section 17 Serial Communication
Interface 3 (SCI3)
17.8.2 Mark State and Break
Sending
404 Amended
When the TXD or TXD2 bit in PMR1 or the TXD_3 bit in
SMCR is 1, the TXD pin is used as an I/O port whose
direction (input or output) and level are determined by
PCR and PDR. This can be used to set the TXD pin to
mark state (high level) or send a break during serial
data transmission. To maintain the communication line
at mark state until TE is set to 1, set both PCR and PDR
to 1 and also set the TXD bit to 1. Then, the TXD pin
becomes an I/O port, and 1 is output from the TXD pin.
To send a break during serial transmission, first set
PCR to 1 and clear PDR to 0, and then set the TXD bit
to 1. At this time, regardless of the current transmission
state, the TXD pin becomes an I/O port, and 0 is output
from the TXD pin.