Datasheet

Section 2 CPU
Rev. 1.50 Sep. 18, 2007 Page 37 of 584
REJ09B0240-0150
2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two to four states. The data bus width is 8 bits or 16
bits depending on the register. For details on the data bus width and number of accessing states of
each register, refer to section 22, List of Registers. Registers with 16-bit data bus width can be
accessed only in words. Registers with 8-bit data bus width can be accessed in bytes or words.
When a register with 8-bit data bus width is accessed in words, two bus cycles for byte access are
generated. In two-state access, the operation timing is the same as that for the on-chip memory.
Figure 2.10 shows the operation timing in three-state access. In four-state access, a wait cycle is
inserted between T
2
state and T
3
state.
T
1
state
Bus cycle
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Read data
Address
Internal
data bus
(write access)
T
2
state T
3
state
Write data
φ
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)