Datasheet

Section 2 CPU
Rev. 1.50 Sep. 18, 2007 Page 39 of 584
REJ09B0240-0150
Reset state
Program halt state
Exception-handling state
Program execution state
Reset cleared
SLEEP instruction executed
Reset
occurs
Interrupt
source
Reset
occurs
Interrupt
source
Exception-
handling
complete
Reset occurs
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or
R4L, which starts from the address indicated by ER5, to the address indicated by ER6. Set R4 or
R4L and ER6 so that the end address of the destination address (value of ER6 + R4 or ER6 + R4L)
does not exceed H'FFFFFF (the value of ER6 must not change from H'FFFFFF to H'000000
during execution).
2.8.3 Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.