Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 45 of 584
REJ09B0240-0150
Section 3 Exception Handling
Exception handling is caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts after the reset state is
cleared by a negation of the RES signal. Exception handling is also started when the watchdog
timer overflows. The exception handling executed at this time is the same as that for a reset by
the RES pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. A vector address
corresponding to a vector number from 0 to 3 which are specified in the instruction code is
generated. Exception handling can be executed at all times in the program execution state,
regardless of the setting of the I bit in CCR.
• Interrupts
External interrupts other than the NMI and internal interrupts other than the address break are
masked by the I bit in CCR, and kept pending while the I bit is set to 1. Exception handling
starts when the current instruction or exception handling ends, if an interrupt is requested.
• Priority level
The priority levels of interrupt sources other than the NMI and address break can be set for
each module by the interrupt control register (ICR).
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority. The
priority level can be set for an interrupt source to which a bit in ICR is assigned. When priority
level 1 (priority is given) is set for an interrupt source other than the NMI and address break, the
execution of the exception handling for the interrupt request has priority that for an interrupt
request whose source is set to priority level 0.