Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 46 of 584
REJ09B0240-0150
Table 3.1 Exception Sources and Vector Address
Related Module Exception Sources
Vector
Number Vector Address ICR Priority
RES pin
Watchdog timer
Reset 0 H'000000 to H'000003  High
 Reserved for system use 1 to 6 H'000004 to H'00001B 
External interrupt
pin
NMI 7 H'00001C to H'00001F 
CPU Trap instruction #0 8 H'000020 to H'000023 
Trap instruction #1 9 H'000024 to H'000027 
Trap instruction #2 10 H'000028 to H'00002B 
Trap instruction #3 11 H'00002C to H'00002F 
Address break Break conditions satisfied 12 H'000030 to H'000033 
CPU Direct transition by executing
the SLEEP instruction
13 H'000034 to H'000037 ICRA7
External interrupt
pin
IRQ0
Low-voltage detection interrupt*
14 H'000038 to H'00003B ICRA6
IRQ1 15 H'00003C to H'00003F ICRA5
IRQ2 16 H'000040 to H'000043 ICRA4
IRQ3 17 H'000044 to H'000047 ICRA3
WKP 18 H'000048 to H'00004B ICRA2
RTC Overflow 19 H'00004C to H'00004F ICRA1
 Reserved for system use 20, 21 H'000050 to H'000053 
Timer V Compare match A
Compare match B
Overflow
22 H'000058 to H'00005B ICRB6
SCI3 Receive data full
Transmit data empty
Transmit end
Receive error
23 H'00005C to H'00005F ICRB5
IIC2 Transmit data empty
Transmit end
Receive data full
Arbitration lost/overrun error
NACK detection
Stop condition detected
24 H'000060 to H'000063 ICRB4
Low