Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 50 of 584
REJ09B0240-0150
3.2.3 Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts.
Bit Bit Name
Initial
Value R/W Description
7 IENDT 0 R/W Direct Transition Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
6 IENTA 0 R/W RTC Interrupt Enable
When this bit is set to 1, an RTC interrupt request is
enabled.
5 IENWP 0 R/W Wakeup Interrupt Enable
This bit is an enable bit for signals WKP5 to WKP0.
When this bit is set to 1, an interrupt request is enabled.
4  1  Reserved
This bit is always read as 1.
3 IEN3 0 R/W IRQ3 Interrupt Enable
When this bit is set to 1, an interrupt request of the
IRQ3 signal is enabled.
2 IEN2 0 R/W IRQ2 Interrupt Enable
When this bit is set to 1, an interrupt request of the
IRQ2 signal is enabled.
1 IEN1 0 R/W IRQ1 Interrupt Enable
When this bit is set to 1, an interrupt request of the
IRQ1 signal is enabled.
0 IEN0 0 R/W IRQ0 Interrupt Enable
When this bit is set to 1, an interrupt request of the
IRQ0 signal is enabled.
A bit in an interrupt enable register to disable the interrupt or a bit in an interrupt flag register must
be cleared while the interrupt is masked (I = 1). If the execution of clearing the above bit and an
interrupt request occurs at the same time while I = 0, the exception handling for the interrupt is
executed after the bit has been cleared.