Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 51 of 584
REJ09B0240-0150
3.2.4 Interrupt Enable Register 2 (IENR2)
IENR2 enables a timer B1 overflow interrupt.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 0  Reserved
These bits are always read as 0.
5 IENTB1 0 R/W Timer B1 Interrupt Enable
When this bit is set to 1, a timer B1 overflow interrupt
request is enabled.
4 to 0  All 1  Reserved
These bits are always read as 1.
A bit in an interrupt enable register to disable the interrupt or a bit in an interrupt flag register must
be cleared while the interrupt is masked (I = 1). If the execution of clearing the above bit and an
interrupt request occurs at the same time while I = 0, the exception handling for the interrupt is
executed after the bit has been cleared.
3.2.5 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for a direct transition interrupt, an RTC interrupt, and IRQ3 to IRQ0
interrupts.
Bit Bit Name
Initial
Value R/W Description
7 IRRDT 0 R/W Direct Transition Interrupt Request Flag
[Setting condition]
When a direct transition is made by executing the
SLEEP instruction while the DTON bit in SYSCR2 is set
to 1.
[Clearing condition]
When writing 0