Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 53 of 584
REJ09B0240-0150
3.2.6 Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 overflow interrupts.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 0 
Reserved
These bits are always read as 0.
5 IRRTB1 0 R/W
Timer B1 Interrupt Request flag
[Setting condition]
When the timer B1 counter overflows
[Clearing condition]
When writing 0
4 to 0  All 1 
Reserved
These bits are always read as 1.
3.2.7 Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 1  Reserved
These bits are always read as 1.
5 IWPF5 0 R/W WKP5 Interrupt Request Flag
[Setting condition]
When the WKP5 pin is specified as an interrupt input
and the specified edge is detected
[Clearing condition]
When writing 0
4 IWPF4 0 R/W WKP4 Interrupt Request Flag
[Setting condition]
When WKP4 pin is specified as an interrupt input and
the specified edge is detected
[Clearing condition]
When writing 0