Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 55 of 584
REJ09B0240-0150
3.2.8 Interrupt Control Registers A to D (ICRA to ICRD)
ICR sets the priority level of an interrupt source other than the NMI and address break. The
correspondence between interrupt requests and bits ICRA to ICRD is shown in table 3.2.
Bit Bit Name
Initial
Value R/W Description
7 to 0 ICRn7 to
ICRn0
All 0* R/W Interrupt Priority Level
0: The corresponding interrupt source is set to interrupt
priority level 0 (nonpriority)
1: The corresponding interrupt source is set to interrupt
priority level 1 (priority)
n = A to D
Note: * The initial values of the reserved bits are also all 0.
Table 3.2 Interrupt request and ICR
Registers
Bit Bit Name ICRA ICRB ICRC ICRD
7 ICRn7 Direct
transition
 Timer B1 Timer RD_0
6 ICRn6 IRQ0,
Low-voltage
detection
Timer V  Timer RD_1
5 ICRn5 IRQ1 SCI3  Timer RD_2
4 ICRn4 IRQ2 IIC2 SCI3_2 Timer RD_3
3 ICRn3 IRQ3   Clock
switching
2 ICRn2 WKP  SCI3_3 
1 ICRn1 RTC  Timer RC 
0 ICRn0   A/D converter 
n = A to D
: Reserved. These bits are always read as 0.