Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 56 of 584
REJ09B0240-0150
3.3 Reset Exception Handling
When the RES signal goes low, all processing halts and this LSI enters the reset state. The internal
state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset.
When the power is turned on, hold the RES signal low until oscillation of the clock pulse
generator settles to ensure that this LSI is reset. To reset this LSI during operation, hold the RES
signal low for a given time. When the RES signal goes high after being held low for the given
time, this LSI starts the reset exception handling. The reset exception handling sequence is shown
in figure 3.1. However, for the reset exception handling sequence of the product with an on-chip
power-on reset circuit, refer to section 20, Band-Gap Regulator, Power-On Reset (Optional), and
Low-Voltage Detection Circuits (Optional).
The reset exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates the vector address for the reset exception handling (from H'000000 to
H'000003), the data in the address is sent to the program counter (PC) as the start address, and
program execution starts from the address.
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
As the external interrupts, there are the NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.
• NMI Interrupt
An NMI interrupt is generated when the edge of the NMI signal is input. The detecting edge is
selected from rising or falling, depending on the setting of the NMIEG bit in IEGR1.
Since the NMI interrupt is given the highest priority level, it can always be accepted regardless
of the setting of the I bit in CCR.
• IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are generated when the edges of the IRQ3 to IRQ0 signals are input.
These four interrupts are given different vector addresses, and the detecting edge of each signal
can be selected from rising or falling, depending on the settings of bits IEG3 to IEG0 in
IEGR1.
When the IRQ3 to IRQ0 pins are specified as an interrupt input by PMR1 and the specified
edge is input, the corresponding bit in IRR1 is set to 1, requesting the interrupt to the CPU.
These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.