Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 57 of 584
REJ09B0240-0150
• WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are generated when the edges of the WKP5 to WKP0 signals are
input. These six interrupts are assigned to the same vector addresses, and the detecting edge for
each signal can be selected from rising or falling, depending on the settings of bits WPEG5 to
WPEG0 in IEGR2.
When pins WKP5 to WKP0 are specified as an interrupt input by PMR5 and the specified
edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt to the CPU.
These interrupts can be masked by setting bit IENWP in IENR1.
Vector fetch
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
RES
Internal
processing
Prefetch of
first program
instruction
φ
(1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002
(2), (4) Start address (contents of reset vector)
(5) Start address
(6) First instruction of program
(1) (3) (5)
(2) (4) (6)
Figure 3.1 Reset Sequence