Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 58 of 584
REJ09B0240-0150
3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to indicate the interrupt request status and the enable bit
to enable or disable the interrupt. For RTC interrupt requests and direct transition interrupt
requests generated by execution of the SLEEP instruction, this function is included in IRR1, IRR2,
IENR1, and IENR2.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting an interrupt to the CPU. These interrupts can be disabled by
clearing the corresponding enable bit to 0.
3.4.3 Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller.
Interrupt operation is described below.
1. If an NMI or an interrupt with its enable bit set to 1 is generated, an interrupt request signal is
sent to the interrupt controller.
2. When multiple interrupt requests are generated, the interrupt controller requests the interrupt
handling with the highest priority level which has been set in ICR to the CPU. Other interrupt
requests are held pending. When the priority levels are the same, the interrupt controller selects
an interrupt request according to the default priority levels shown in table 3.1.
3. The CPU accepts the NMI and address break regardless of the setting of the I bit. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after execution of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
stack status at this time is shown in figure 3.3. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
5. Then, the I bit in CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handler. Then a program starts
executing from the address indicated in PC.