Datasheet

Section 3 Exception Handling
Rev. 1.50 Sep. 18, 2007 Page 59 of 584
REJ09B0240-0150
Figure 3.2 shows the interrupt acceptance flowchart. Figure 3.4 shows a typical interrupt sequence
where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
Program execution state
Interrupt generated
NMI
Interrupt set
to priority level 1
Direct
transition
Direct
transition
IRQ0
Clock
switching
interrupt
Clock
switching
interrupt
IRQ0
I = 0
PC and CCR saved
I ← 1
Vector address read
Execution branched to
interrupt handler
Yes
No
Yes
Yes
Yes
No
No
Yes
No
Yes
No
Yes
Yes
No
No
Yes
Yes
No
Pending
Address break
No
Yes
Figure 3.2 Interrupt Acceptance Flowchart