To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/36912 Group, H8/36902 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36912F H8/36902F H8/36912 H8/36911 H8/36902 H8/36901 H8/36900 HD64F36912G HD64F36902G HD64336912G HD64336911G HD64336902G HD64336901G HD64336900G Rev.3.00 2006.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/36912 Group and H8/36902 Group are single-chip microcomputers made up of the highspeed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36912 Group and H8/36902 Group in the design of application systems.
Notes: When using an on-chip emulator (E7, E8) for H8/36912, H8/36902 program development and debugging, the following restrictions must be noted. The NMI pin is reserved for the E7 or E8, and cannot be used. Area H'2000 to H'2FFF is used by the E7 or E8, and is not available to the user. Area H'F980 to H'FD7F must on no account be accessed. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ....................................................................................
3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 51 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 52 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53 Reset Exception Handling .......................
5.7 Usage Notes ........................................................................................................................ 84 5.7.1 Note on Resonators............................................................................................. 84 5.7.2 Notes on Board Design ....................................................................................... 84 Section 6 Power-Down Modes ............................................................................85 6.1 6.2 6.3 6.4 6.
Section 9 I/O Ports............................................................................................. 117 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Port 1................................................................................................................................. 117 9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 118 9.1.2 Port Control Register 1 (PCR1) ......................................................................
10.3 10.4 Operation .......................................................................................................................... 142 10.3.1 Interval Timer Operation .................................................................................. 142 10.3.2 Auto-Reload Timer Operation .......................................................................... 142 Timer B1 Operating Modes ..............................................................................................
12.6 12.5.4 Timing of Counter Clearing by Compare Match .............................................. 183 12.5.5 Buffer Operation Timing .................................................................................. 184 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 185 12.5.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... 186 12.5.8 Timing of Status Flag Clearing......................................................
14.7 14.8 14.6.1 Multiprocessor Serial Data Transmission ......................................................... 229 14.6.2 Multiprocessor Serial Data Reception .............................................................. 231 Interrupts........................................................................................................................... 235 Usage Notes ...................................................................................................................... 236 14.8.
Section 16 A/D Converter ................................................................................. 273 16.1 16.2 16.3 16.4 16.5 16.6 Features............................................................................................................................. 273 Input/Output Pins.............................................................................................................. 275 Register Description .............................................................................
20.3 20.4 20.5 20.2.1 Power Supply Voltage and Operating Ranges .................................................. 314 20.2.2 DC Characteristics ............................................................................................ 316 20.2.3 AC Characteristics ............................................................................................ 321 20.2.4 A/D Converter Characteristics .......................................................................... 325 20.2.
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Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 1.6 Overview Internal Block Diagram of H8/36912 Group................................................................. 3 Internal Block Diagram of H8/36902 Group................................................................. 4 Pin Arrangement of H8/36912 Group (FP-32A) ........................................................... 5 Pin Arrangement of H8/36902 Group (FP-32A) ......................................................
Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 State Transition of System Clock ................................................................................ 75 Figure 5.3 Flowchart of Clock Switching On-chip Oscillator Clock to External Clock (1) ........ 76 Figure 5.4 Flowchart of Clock Switching External Clock to On-chip Oscillator Clock (2) ......... 77 Figure 5.
Figure 11.6 TMOV Output Timing ............................................................................................ 154 Figure 11.7 Clear Timing by Compare Match............................................................................ 154 Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 155 Figure 11.9 Pulse Output Example .............................................................................................
Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 191 Figure 13.2 Watchdog Timer Operation Example...................................................................... 195 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Serial Communication Interface 3 (SCI3) Block Diagram of SCI3...........................................................................................
Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 259 Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 260 Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 261 Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 262 Figure 15.
Figure 20.5 SCK3 Input Clock Timing ...................................................................................... 347 Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 348 Figure 20.7 Output Load Circuit ................................................................................................ 348 Appendix Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 379 Figure B.
Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.4 Table 7.5 Table 7.6 Reprogram Data Computation Table .................................................................... 109 Additional-Program Data Computation Table ...................................................... 109 Programming Time ............................................................................................... 109 Section 10 Timer B1 Table 10.1 Timer B1 Operating Modes ..................................................................................
Table 20.5 Table 20.6 Table 20.7 Table 20.8 Table 20.9 Table 20.10 Table 20.11 Table 20.12 Table 20.12 Table 20.13 Table 20.14 Table 20.15 Table 20.16 Table 20.17 Table 20.18 Table 20.19 Table 20.20 Serial Interface (SCI3) Timing ............................................................................. 324 A/D Converter Characteristics .............................................................................. 325 Watchdog Timer Characteristics........................................................
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Section 1 Overview Section 1 Overview 1.
Section 1 Overview • General I/O ports Eighteen I/O pins, including five large-current ports (IOL = 20 mA, @VOL = 1.5 V, −IOH = 4 mA, @VOH = Vcc − 1.0 V) Four input only pins (also used for analog input) • On-chip oscillator Frequency accuracy: 8MHz ±1% (Typ.) Vcc = 5.0 V, Ta = 25°C (Flash memory version): 8MHz ±3% Vcc = 4.0 to 5.0 V, Ta = −20 to 75°C 10MHz ±4% (Typ.) Vcc = 4.0 to 5.
Section 1 Overview (OSC1) (OSC2) On-chip oscillator CPU H8/300H Timer W SCI3 Port 7 RAM Port 8 Port 2 ROM Timer V IIC2 Timer B1 Watchdog timer A/D converter POR & LVD P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Port B AVCC PC0/OSC1 PC1/OSC2/CLKOUT Port C P76/TMOV P75/TMCIV P74/TMRIV PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 P57/SCL P56/SDA P55/WKP5/ADTRG Port 5 P22/TXD P21/RXD P20/SCK3 Port 1 Data bus (lower) P17/IRQ3/TRGV P14/IRQ0 Address bus System clock generator E10T
(OSC1) (OSC2) On-chip oscillator CPU H8/300H Port 7 RAM Timer W SCI3 Timer V Watchdog timer A/D converter POR & LVD Port B AVCC PC0/OSC1 PC1/OSC2/CLKOUT Port C Port 8 Port 2 ROM PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 P57 P56 P55/WKP5/ADTRG Port 5 P22/TXD P21/RXD P20/SCK3 Port 1 Data bus (lower) P17/IRQ3/TRGV P14/IRQ0 Address bus System clock generator E10T_0* E10T_1* E10T_2* Data bus (upper) NMI TEST RES VCC VCL VSS Section 1 Overview Note: * Can also be used for the E
Section 1 Overview P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI P22/TXD P21/RXD P20/SCK3 P55/WKP5/ADTRG 24 23 22 21 20 19 18 17 Pin Arrangement P84/FTIOD 25 16 P14/IRQ0 P74/TMRIV 26 15 P56/SDA P75/TMCIV 27 14 P57/SCL P76/TMOV 28 13 E10T_2* 12 E10T_1* H8/36912 Group (Top view) 7 8 VCL 9 PC0/OSC1 32 6 PB0/AN0 PC1/OSC2/CLKOUT P17/IRQ3/TRGV 5 10 Vss 31 4 PB1/AN1 TEST E10T_0* 3 11 RES 30 2 PB2/AN2/ExtD Vcc 29 1 PB3/AN3/ExtU AVcc 1.
P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI P22/TXD P21/RXD P20/SCK3 P55/WKP5/ADTRG 24 23 22 21 20 19 18 17 Section 1 Overview P84/FTIOD 25 16 P14/IRQ0 P74/TMRIV 26 15 P56 P75/TMCIV 27 14 P57 P76/TMOV 28 13 E10T_2* 12 E10T_1* H8/36902 Group (Top view) 7 8 PC0/OSC1 VCL 9 6 32 PC1/OSC2/CLKOUT PB0/AN0 5 P17/IRQ3/TRGV Vss 10 4 31 TEST PB1/AN1 3 E10T_0* RES 11 2 30 Vcc PB2/AN2/ExtD 1 29 AVcc PB3/AN3/ExtU NMI Note: * Can also be used for the E7 or E8 emu
Section 1 Overview PB3/AN3/ExtU 1 32 P76/TMOV PB2/AN2/ExtD 2 31 P75/TMCIV PB1/AN1 3 30 P74/TMRIV PB0/AN0 4 29 P84/FTIOD AVcc 5 28 P83/FTIOC Vcc 6 27 P82/FTIOB RES 7 26 P81/FTIOA TEST 8 H8/36912 Group 25 P80/FTCI Vss 9 (Top view) 24 P22/TXD PC1/OSC2/CLKOUT 10 23 P21/RXD PC0/OSC1 11 22 P20/SCK3 VCL 12 21 P55/WKP5/ADTRG NMI 13 20 P14/IRQ0 P17/IRQ3/TRGV 14 19 P56/SDA E10T_0* 15 18 P57/SCL E10T_1* 16 17 E10T_2* Note: * Can also be used for the E7
Section 1 Overview PB3/AN3/ExtU 1 32 P76/TMOV PB2/AN2/ExtD 2 31 P75/TMCIV PB1/AN1 3 30 P74/TMRIV PB0/AN0 4 29 P84/FTIOD AVcc 5 28 P83/FTIOC Vcc 6 27 P82/FTIOB RES 7 26 P81/FTIOA TEST 8 H8/36902 Group 25 P80/FTCI Vss 9 (Top view) 24 P22/TXD PC1/OSC2/CLKOUT 10 23 P21/RXD PC0/OSC1 11 22 P20/SCK3 VCL 12 21 P55/WKP5/ADTRG NMI 13 20 P14/IRQ0 P17/IRQ3/TRGV 14 19 P56 E10T_0* 15 18 P57 E10T_1* 16 17 E10T_2* Note: * Can also be used for the E7 or E8 e
Section 1 Overview 1.4 Table 1.1 Pin Functions Pin Functions Pin No. Type Symbol FP-32D, 32P4B FP-32A I/O Functions Power source VCC 6 2 Input Power supply pin. Connect this pin to the system power supply. VSS 9 5 Input Ground pin. Connect this pin to the system power supply (0 V). AVCC 5 1 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. VCL 12 8 Input Internal step-down power supply pin.
Section 1 Overview Pin No. Type Symbol FP-32D, 32P4B FP-32A I/O Functions Timer V TMOV 32 28 Output TMOV is an output pin for waveforms generated by the output compare function.
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. The following two figures show the memory map, respectively.
Section 2 CPU H8/36911 H8/36901 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector H8/36900 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector On-chip ROM (2 kbytes) On-chip ROM (4 kbytes) H'07FF H'0FFF Not used Not used H'F600 H'F77F Internal I/O register H'F600 H'F77F Internal I/O register Not used Not used H'FE80 H'FE80 On-chip RAM user area (256 bytes) H'FF7F H'FF80 On-chip RAM user area (256 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF Internal I/O register H'FF
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the stack. Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute.
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB 0 LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 3.00 Sep.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address registers (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd), EXR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.4.
Section 2 CPU (3) Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.
Section 2 CPU (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.
Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly.
Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU (1) Bit Manipulation for Two Registers Assigned to the Same Address Example 1: Bit manipulation for the timer load register and timer counter (Applicable to timer B1, not available for the H8/36902 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address.
Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. [Prior to executing BSET] MOV.B MOV.B MOV.B #80, R0L, R0L, R0L @RAM0 @PDR5 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR5. [Prior to executing BCLR] MOV.B MOV.B MOV.
Section 2 CPU Rev. 3.00 Sep.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling Relative Module Exception Sources Vector Number Vector Address Priority Address break Break conditions satisfied 12 H'0018 to H'0019 High CPU Direct transition by executing the SLEEP instruction 13 H'001A to H'001B External interrupt pin IRQ0, low-voltage detection interrupt 14 H'001C to H'001D Reserved for system use 15, 16 H'001E to H'0021 External interrupt pin IRQ3 17 H'0022 to H'0023 WKP 18 H'0024 to H'0025 Reserved for system use 19, 20
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • • • • • • • Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register 2 (IRR2) Wakeup interrupt flag register (IWPR) 3.2.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5 pins. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved 5 WPEG5 0 R/W WKP5 Edge Select These bits are always read as 1. 0: Falling edge of WKP5 (ADTRG) pin input is detected 1: Rising edge of WKP5 (ADTRG) pin input is detected 4 to 0 All 0 Reserved These bits are always read as 0. 3.2.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 0 IEN0 0 R/W IRQ0 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled. 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables timer B1 interrupts. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0. 6 0 R/W Reserved Although this bit is readable/writable, it should not be set to 1.
Section 3 Exception Handling 3.2.5 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag [Setting condition] • When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1. [Clearing condition] • 6 0 When IRRDT is cleared by writing 0 Reserved This bit is always read as 0.
Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 interrupt requests. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0. 6 Reserved 5 IRRTB1 0 R/W Timer B1 Interrupt Request Flag [Setting condition] • When timer B1 overflows [Clearing condition] • 4 to 0 All 1 When IRRTB1 is cleared by writing 0 Reserved These bits are always read as 1. 3.2.
Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low for the specified period. To reset the chip during operation, hold the RES pin low for the specified period.
Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts. (1) NMI Interrupt NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and can always be accepted without depending on the I bit value in CCR. (2) IRQ3 and IRQ0 Interrupts IRQ3 and IRQ0 interrupts are requested by input signals to the IRQ3 and IRQ0 pins.
Section 3 Exception Handling ~ Reset cleared ~ Internal address bus (1) (2) ~ φ ~ RES Initial program instruction prefetch Vector fetch Internal processing Internal write signal ~ Internal data bus (16 bits) ~ Internal read signal (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.
Section 3 Exception Handling 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1.
Section 3 Exception Handling Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
Section 3 Exception Handling 3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 23 15 to 37 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note: * EEPMOV instruction is not included. Rev. 3.00 Sep.
REJ09B0105-0300 Rev. 3.00 Sep. 14, 2006 Page 60 of 408 Figure 3.3 Interrupt Sequence (2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 3 Exception Handling Rev. 3.00 Sep.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare Condition Select 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] • When the condition set in ABRKCR is satisfied [Clearing condition] • 6 ABIE 0 R/W When 0 is written after ABIF=1 is read Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) consists of an external oscillator, an onchip oscillator, a duty correction circuit, a clock select circuit, and system clock dividers. Figure 5.1 shows a block diagram of the clock pulse generator.
Section 5 Clock Pulse Generators 5.1 Features • Choice of two clock sources On-chip oscillator clock External oscillator clock • Choice of two types of on-chip oscillation frequency by the user software 8MHz 10MHz • Frequency trimming Users can adjust the on-chip oscillation frequency by rewriting the trimming registers. • Interrupt can be requested to the CPU when the system clock is changed from the external clock to the on-chip oscillator clock. Rev. 3.00 Sep.
Section 5 Clock Pulse Generators 5.2 Register Descriptions Clock oscillators are controlled by the following registers. • • • • RC control register (RCCR) RC trimming data protect register (RCTRMDPR) RC trimming data register (RCTRMDR) Clock control/status register (CKCSR) 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator.
Section 5 Clock Pulse Generators 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Bit Bit Name Initial Value R/W Description 7 WRI 1 W Write Inhibit Only when writing 0 to this bit, this register can be written to. This bit is always read as 1.
Section 5 Clock Pulse Generators Initial Value Bit Bit Name 4 TRMDRWE 0 R/W Description R/W Trimming Date Register Write Enable This register can be written to when the LOCKDW bit is 0 and this bit is 1.
Section 5 Clock Pulse Generators 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state. Bit Bit Name Initial Value R/W Description 7 PMRC1 0 R/W Port C Function Select 1 and 0 6 PMRC0 0 R/W PMRC1 PMRC0 PC1 PC0 0 I/O 5 0 R/W 0 I/O 1 0 CLKOUT I/O 0 1 I/O OSC1 (external clock input) 1 1 OSC2 OSC1 Reserved Although this bit is readable/writable, it should not be set to 1.
Section 5 Clock Pulse Generators 5.3 System Clock Select Operation Figure 5.2 shows the state transition of the system clock.
Section 5 Clock Pulse Generators 5.3.1 Clock Control Operation The LSI system clock is generated by the on-chip oscillator clock after a reset. The on-chip oscillator clock is switched to the external clock by the user software.
Section 5 Clock Pulse Generators LSI operates on external clock [1] When 0 is written to the OSCSEL bit, this LSI switches the external clock to the on-chip oscillator clock after the φ stop duration. Seven rising edges of the φRC clock after the OSCSEL bit becomes 0 are included in the φ stop duration. [2] Writing 0 to PMRC0 stops the external oscillation.
Section 5 Clock Pulse Generators 5.3.2 Clock Change Timing The timing for changing clocks are shown in figures 5.5 and 5.6.
Section 5 Clock Pulse Generators φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF φ halt* External clock operation Wait for external oscillation settling On-chip oscillator clock operation Nwait [Legend] φOSC: External clock φRC: On-chip oscillator clock φ: System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR CKSWIF: Bit 2 in CKCSR Note: * The φ halt duration is the duration from the timing when the φ clock stops to the seventh rising edge of the
Section 5 Clock Pulse Generators 5.4 Trimming of On-chip Oscillator Frequency Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the input capture function in internal timer W. An example of trimming flow and a timing chart are shown in figures 5.7 and 5.8, respectively.
Section 5 Clock Pulse Generators φRC FTIOA input capture input tA (µs) Timer W TCNT GRA M-1 M N GRC M+1 M N Capture 1 M+α M+α M Capture 2 Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below. Since the input-capture input is sampled by the φRC clock, the calculated result may include a sampling error of ±1 cycle of the φRC clock.
Section 5 Clock Pulse Generators 5.5 External Oscillators This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.3, System Clock Select Operation. 5.5.1 Connecting Crystal Resonator Figure 5.9 shows an example of connecting a crystal resonator.
Section 5 Clock Pulse Generators 5.5.2 Connecting Ceramic Resonator Figure 5.11 shows an example of connecting a ceramic resonator. C1 PC0/OSC1 C2 PC1/OSC2/CLKOUT C1 = C 2 = 5 to 30 pF Figure 5.11 Example of Connection to Ceramic Resonator 5.5.3 External Clock Input Method To use the external clock, input the external clock on pin OSC1. Figure 5.12 shows an example of connection. The duty cycle of the external clock signal must be 45 to 55%.
Section 5 Clock Pulse Generators 5.7 Usage Notes 5.7.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable values should be determined in consultation with the resonator element manufacturer.
Section 6 Power-Down Modes Section 6 Power-Down Modes For operating modes after a reset, this LSI has not only a normal active mode but also three power-down modes in which power consumption is significantly reduced. In addition, there is also a module standby function which reduces power consumption by individually stopping on-chip peripheral modules. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock.
Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. 0: Shifts to sleep mode. 1: Shifts to standby mode. For details, see table 6.2.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Wait Time Bit Name Operating Frequency STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 5 MHz 4 MHz 2.5 MHz 2 MHz 0 0 0 8,192 states 0.8 1.0 1.6 2.0 3.3 4.1 0 0 1 16,384 states 1.6 2.0 3.3 4.1 6.6 8.2 0 1 0 32,768 states 3.3 4.1 6.6 8.2 13.1 16.4 0 1 1 65,536 states 6.6 8.2 13.1 16.4 26.2 32.8 1 0 0 131,072 states 13.1 16.4 26.2 32.8 52.4 65.5 1 0 1 1,024 states 0.10 0.13 0.21 0.26 0.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection This bit specifies the mode to be entered after executing the SLEEP instruction, as well as the SSBY bit in SYSCR1. For details, see table 6.2. 6 0 Reserved This bit is always read as 0.
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W 7 0 Description Reserved This bit is always read as 0. 6 MSTIIC 0 R/W IIC2 Module Standby IIC2 enters standby mode when this bit is set to 1. 5 MSTS3 0 R/W SCI3 Module Standby 4 MSTAD 0 R/W A/D Converter Module Standby SCI3 enters standby mode when this bit is set to 1.
Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 to 5 All 0 Reserved These bits are always read as 0. 4 MSTTB1 0 R/W Timer B1 Module Standby Timer B1 enters standby mode when this bit is set to 1. 3 to 0 All 0 Reserved These bits are always read as 0. Rev. 3.00 Sep.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition from active mode to active mode changes the operating frequency.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and the CPU starts interrupt exception handling. Sleep mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of CPU registers, the on-chip RAM, and some on-chip peripheral module registers are retained. The I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator starts functioning.
Section 6 Power-Down Modes 6.5 Module Standby Function The module standby function can be set to any peripheral module. In module standby mode, the clock supply to the specified module stops and the module enters the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module in MSTCR1 and MSTCR2 to 1 and cancels the mode by clearing the bit to 0. Rev. 3.00 Sep.
Section 6 Power-Down Modes Rev. 3.00 Sep.
Section 7 ROM Section 7 ROM The features of the 12-kbyte (including 4 kbytes as the E7 or E8 control program area) flash memory built into the HD64F36912G and HD64F36902G are summarized below. • Programming/erase methods The flash memory is programmed in 64-byte units at a time. Erase is performed in singleblock units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 4 kbytes × 2 blocks. To erase the entire flash memory, each block must be erased in turn.
Section 7 ROM Erase unit H'0000 H'0001 H'0002 H'0040 H'0041 H'0042 H'007F H'03C0 H'03C1 H'03C2 H'03FF H'0400 H'0401 H'0402 H'0440 H'0441 H'0442 H'047F H'07C0 H'07C1 H'07C2 H'07FF H'0800 H'0801 H'0802 H'0840 H'0841 H'0842 H'087F H'0BC0 H'0BC1 H'0BC2 H'0BFF H'0C00 H'0C01 H'0C02 H'0C40 H'0C41 H'0C42 Programming unit: 64 bytes H'003F 1 kbyte Erase unit Programming unit: 64 bytes H'043F 1 kbyte Erase unit Programming unit: 64 bytes H'083F 1 kbyte Erase unit Pr
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing.
Section 7 ROM Bit Bit Name Initial Value R/W Description 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory changes to program mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 — Reserved These bits are always read as 0. 5 EB5 0 R/W When this bit is set to 1, 4 kbytes of H'2000 to H'2FFF will be erased.
Section 7 ROM 7.3 On-Board Programming Modes There is a mode for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends.
Section 7 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary.
Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 8 MHz (on-chip oscillator clock) 4,800 bps 8 MHz (on-chip oscillator clock) 2,400 bps 8 MHz (on-chip oscillator clock) Rev. 3.00 Sep.
Section 7 ROM 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM START Write pulse application subroutine *2 Disable WDT Apply Write Pulse Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 64-byte program data in program data area and reprogram data area *1 Wait 50 µs n=1 Set P bit in FLMCR1 m= 0 Wait (Wait time = Programming time) Clear P bit in FLMCR1 Write 64-byte data in RAM reprogram data area consecutively to flash memory Wait 5 µs Apply Write pulse Clear PSU bit in FLMCR1 Set PV bit in FLMCR1 Wait 4 µs Wait 5
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7.
Section 7 ROM 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1.
Section 7 ROM Erase start *2 Disable WDT SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 Wait 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs *1 n←n+1 Read verify data No Verify data = all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes No
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset. Rev. 3.00 Sep.
Section 7 ROM Rev. 3.00 Sep.
Section 8 RAM Section 8 RAM The H8/36912F and H8/36902F have 1536 bytes, the H8/36912 and H8/36902 have 512 bytes, and the H8/36911, H8/36901, and H8/36900 have 256 bytes of on-chip high-speed static RAM, respectively. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Section 8 RAM Rev. 3.00 Sep.
Section 9 I/O Ports Section 9 I/O Ports The LSI of the H8/36912 Group and H8/36902 Group has 18 general I/O ports. Port 8 (P84 to P80) is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W P17/IRQ3/TRGV Pin Function Switch Selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6, 5 All 0 Reserved These bits are always read as 0. 4 IRQ0 0 R/W P14/IRQ0 Pin Function Switch Selects whether pin P14/IRQ0 is used as P14 or as IRQ0.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 5 When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bits 6, 5, and 3 to 0 are reserved.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W Only bits for which PCR1 is cleared are valid. 6 1 5 1 4 PUCR14 0 R/W The pull-up MOS of the P17 and P14 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 3 1 2 1 1 1 0 1 9.
Section 9 I/O Ports • P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function 0 P14 input pin 1 P14 output pin X IRQ0 input pin Setting value 0 1 [Legend] X: Don't care 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. P22/TXD Port 2 P21/RXD P20/SCK3 Figure 9.
Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Bit Bit Name Initial Value R/W Description 7 to 3 Reserved 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W When each of the port 2 pins, P22 to P20, functions as an general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.2.
Section 9 I/O Ports 9.2.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports 9.3 Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin*, A/D trigger input pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface has priority for functions of the P57/SCL and P56/SDA pins. Note: * Supported only by the H8/36912 Group. P57/SCL Port 5 P56/SDA P55/WKP5/ADTRG Figure 9.3 Port 5 Pin Configuration Port 5 has the following registers.
Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG. 0: General I/O port 1: WKP5/ADTRG input pin 4 to 0 All 0 Reserved These bits are always read as 0. 9.3.
Section 9 I/O Ports 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Bit Bit Name Initial Value R/W Description 7 P57 0 R/W These bits store output data for port 5 pins. 6 P56 0 R/W 5 P55 0 R/W If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read. If PDR5 is read while PCR5 bits are cleared to 0, the pin states are read regardless of the value stored in PDR5. 4 to 0 All 1 Reserved These bits are always read as 1.
Section 9 I/O Ports 9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P57/SCL pin Register ICCR PCR5 Bit Name ICE PCR57 Pin Function 0 P57 input pin 1 P57 output pin X SCL I/O pin* Setting value 0 1 [Legend] X: Don't care Note: As the SCL output form is NMOS open-drain, direct bus drive is enabled. * Supported only by the H8/36912 Group.
Section 9 I/O Ports 9.4 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of the P76/TMOV pin. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input ports that are connected to the timer V regardless of the register setting of port 7. P76/TMOV Port 7 P75/TMCIV P74/TMRIV Figure 9.4 Port 7 Pin Configuration Port 7 has the following registers.
Section 9 I/O Ports 9.4.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Bit Name Initial Value R/W 7 1 Description Reserved This bit is always read as 1. 6 P76 0 R/W These bits store output data for port 7 pins. 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 is read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7.
Section 9 I/O Ports • P75/TMCIV pin Register PCR7 Bit Name PCR75 Setting value 0 1 Pin Function P75 input/TMCIV input pin P75 output/TMCIV input pin • P74/TMRIV pin Register PCR7 Bit Name PCR74 Setting value 0 1 9.5 Pin Function P74 input/TMRIV input pin P74 output/TMRIV input pin Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5.
Section 9 I/O Ports 9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Bit Bit Name Initial Value R/W 7 to 5 Reserved 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W When each of the port 8 pins, P84 to P80, functions as an general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 1 PCR81 0 W 0 PCR80 0 W 9.5.
Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • P82/FTIOB pin Register TMRW Bit Name PWMB Setting value 0 1 TIOR0 PCR8 IOB2 IOB1 IOB0 PCR82 Pin Function 0 0 0 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin 0 0 1 X FTIOB output pin 0 1 X X FTIOB output pin 1 X X 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin X PWM output pin X X X [Legend] X: Don't care • P81/FTIOA pin Register Bit Name TIOR0 IOA2 Setting value 0 PCR8 IOA1 IOA0 PCR81 Pin Function 0 0 0 P81 input/F
Section 9 I/O Ports 9.6 Port B Port B is an input port also functioning as an A/D converter analog input pin and LVD external comparison voltage input pin. Each pin of the port B is shown in figure 9.6. PB3/AN3/ExtU PB2/AN2/ExtD Port B PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.6.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
Section 9 I/O Ports 9.6.2 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • PB0/AN0 pin Register ADCSR Bit Name CH2 SCAN CH1 CH0 Pin Function Setting value 0 0 0 0 AN0 input pin 0 1 X X Other than the above values PB0 input pin [Legend] X: Don't care 9.7 Port C Port C is a general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.7. The register setting of CKCSR has priority for functions of the pins for both uses. Port C PC1/OSC2/CLKOUT PC0/OSC1 Figure 9.
Section 9 I/O Ports 9.7.1 Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C. Bit Bit Name Initial Value R/W 7 to 2 Reserved 1 PCRC1 0 W 0 PCRC0 0 W When each of the port C pins, PC1 and PC0, functions as an general I/O port, setting a PCRC bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.7.
Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 10 Timer B1 Section 10 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1. 10.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) • An interrupt is generated when the counter overflows.
Section 10 Timer B1 10.2 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 10.2.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock.
Section 10 Timer B1 10.2.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. 10.2.
Section 10 Timer B1 10.3 Operation 10.3.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The operating clock of timer B1 is selected from seven internal clock signals output by prescaler S. The selection is made by the TMB12 to TMB10 bits in TMB1.
Section 10 Timer B1 10.4 Timer B1 Operating Modes Table 10.1 shows the timer B1 operating modes. Table 10.1 Timer B1 Operating Modes Operating Mode Reset Active Sleep Subsleep Standby TCB1 Reset Functions Functions Halted Halted Auto-reload Reset Functions Functions Halted Halted Reset Functions Retained Retained Retained TMB1 Interval Rev. 3.00 Sep.
Section 10 Timer B1 Rev. 3.00 Sep.
Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of timer V. 11.
Section 11 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Output control TCSRV Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B
Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 11.3 Register Descriptions Time V has the following registers.
Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1.
Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 1 Reserved This bit is always read as 1. 0 ICKS0 0 R/W Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2. 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals.
Section 11 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 11.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 11.4 OVF Set Timing Rev. 3.00 Sep.
Section 11 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 11.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 11.7 Clear Timing by Compare Match Rev. 3.00 Sep.
Section 11 Timer V φ TMRIV (External counter reset input pin) TCNTV reset signal N–1 TCNTV N H'00 Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
Section 11 Timer V TCORA write cycle by CPU T2 T1 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. 3.00 Sep.
Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 12.
Section 12 Timer W Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer W. Table 12.
Section 12 Timer W Internal clock: φ φ/2 φ/4 φ/8 External clock: FTCI FTIOA Clock selector FTIOB FTIOC Control logic FTIOD Comparator TIOR TSRW TIERW TCRW TMRW GRD GRC GRB Bus interface [Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW: GRA TCNT IRRTW Internal data bus Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits
Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.
Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 1 Reserved This bit is always read as 1. 5 BUFEB 0 R/W Buffer Operation B Selects the GRD function.
Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 CKS2 0 R/W Clock Select 2 to 0 5 CKS1 0 R/W Select the TCNT clock source.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 0 TOA 0 R/W Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* [Legend] X: Don't care Note: * The change of the setting is immediately reflected in the output value. 12.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request.
Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] • When TCNT overflows from H'FFFF to H'0000 [Clearing condition] • 6 to 4 All 1 Read OVF when OVF = 1, then write 0 in OVF Reserved These bits are always read as 1.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition] • 0 IMFA 0 R/W Read IMFB when IMFB = 1, then write 0 in IMFB Input Capture/Compare Match Flag A [Setting conditions] • TCNT = GRA when GRA functions as an output co
Section 12 Timer W 12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1. 6 IOB2 0 R/W I/O Control B2 Selects the GRB function.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IOA1 0 R/W I/O Control A1 and A0 0 IOA0 0 R/W When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1X: Input capture at rising and falling edges of the FTIOA pin [L
Section 12 Timer W Bit Bit Name Initial Value R/W Description 5 IOD1 0 R/W I/O Control D1 and D0 4 IOD0 0 R/W When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1, 00: Input capture at rising edge at the FTIOD pin 01: Input capture at falling edge at the FTIOD pin 1X: Input capture at rising and falling edges at the FTIOD pin 3
Section 12 Timer W 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
Section 12 Timer W 12.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 12.
Section 12 Timer W Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic counting. TCNT value GRA H'0000 Time CTS bit Flag cleared by software IMFA Figure 12.
Section 12 Timer W Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF GRA GRB Time H'0000 FTIOA Toggle output FTIOB Toggle output Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 12.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
Section 12 Timer W Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
Section 12 Timer W TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1). TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.
Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
Section 12 Timer W Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously.
Section 12 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB Duty 100% Figure 12.
Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly. φ Internal clock Rising edge TCNT input clock TCNT N N+1 N+2 Figure 12.
Section 12 Timer W 12.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 12.16 shows the output compare timing.
Section 12 Timer W 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. φ Input capture input Input capture signal N–1 TCNT N N+1 N+2 N GRA to GRD Figure 12.17 Input Capture Input Signal Timing 12.5.
Section 12 Timer W 12.5.5 Buffer Operation Timing Figures 12.19 and 12.20 show the buffer operation timing. φ Compare match signal TCNT N GRC, GRD M N+1 M GRA, GRB Figure 12.19 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 12.20 Buffer Operation Timing (Input Capture) Rev. 3.00 Sep.
Section 12 Timer W 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count).
Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal TCNT N N GRA to GRD IMFA to IMFD IRRTW Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture 12.5.
Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle.
Section 12 Timer W TCNT write cycle T2 T1 φ TCNT address Address Write signal Counter clear signal N TCNT H'0000 Figure 12.24 Contention between TCNT Write and Clear Clock before switching Clock after switching Count clock TCNT N N+1 N+2 N+3 The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12.25 Internal Clock Switching and TCNT Operation Rev. 3.00 Sep.
Section 12 Timer W TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low; the FTIOB signal remains high.
Section 12 Timer W Rev. 3.00 Sep.
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. WDT dedicated internal oscillator φ CLK TCSRWD PSS TCWD Internal data bus The block diagram of the watchdog timer is shown in figure 13.1.
Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 13 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 1 R/W Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The watchdog timer is enabled in the initial state. When the watchdog timer is not used, clear the WDON bit to 0.
Section 13 Watchdog Timer 13.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1.
Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 φRC clock cycles. As TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value.
Section 13 Watchdog Timer Rev. 3.00 Sep.
Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) This LSI includes serial communication interface 3 (SCI3). SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Section 14 Serial Communication Interface 3 (SCI3) Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors SCK3 External clock Baud rate generator BRC Internal clock (φ/64,φ/16, φ/4, φ) BRR Clock Transmit/receive control circuit SCR3 SSR SPMR TXD Noise filter circuit RXD TSR TDR RSR RDR Internal data bus SMR Interrupt request (TEI, TXI, RXI, ERI) [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data reg
Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 Input/output SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 14.3 Register Descriptions SCI3 has the following registers for each channel.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.3.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TDRE af
Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (highspeed) mode. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.
Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 3.6864 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.
Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 8 9.8304 10 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 150 2 103 0.16 2 127 0.00 2 129 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 9600 0 25 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) 2 4 8 10 Bit Rate (bit/s) n N n N n N n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — — 500 1 249 2 124 2 249 — — 1k 1 124 1 249 2 124 — — 2.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.9 Sampling Mode Register (SPMR) SPMR controls the serial communication function. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved These bits are always read as 1. 2 STDSPM 1 R/W Noise Filter Function Select Selects the noise filter function for the RXD pin in asynchronous mode. 0: Noise filter circuit is enabled 1: Noise filter circuit is disabled 1, 0 All 1 Reserved These bits are always read as 1.
Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.3 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.6 shows an example of operation for transmission in asynchronous mode. In transmission, SCI3 operates as described below. 1. SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial reception, SCI3 operates as described below. 1. SCI3 monitors the communication line. If a start bit is detected, SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample flow chart for serial data reception. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.10 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.2 SCI3 Initialization Before transmitting and receiving data, SCI3 should be initialized as described in a sample flowchart in figure 14.5. 14.5.3 Serial Data Transmission Figure 14.11 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, SCI3 operates as described below. 1.
Section 14 Serial Communication Interface 3 (SCI3) Figure 14.12 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, SCI3 operates as described below. 1. 2. 3. 4. SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. SCI3 stores the receive data in RSR.
Section 14 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.14 shows a sample flow chart for serial data reception. Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.15 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 14 Serial Communication Interface 3 (SCI3) [1] Start transmission/reception Read TDRE flag in SSR [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 Yes No Read RDRF flag in SSR [2] No [4] RDRF = 1 Yes Overrun error processing Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) 14.6.1 Multiprocessor Serial Data Transmission Figure 14.17 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode. Rev. 3.00 Sep.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR [3] Write transmit data to TDR Yes [2] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
Section 14 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Sep.
Section 14 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 User processing RXI interrupt request is not generated, and RDR retains its state RDR data read When data is not this station's ID, MPIE is set to 1 again (a
Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.8.
Section 14 Serial Communication Interface 3 (SCI3) 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.20.
Section 14 Serial Communication Interface 3 (SCI3) Rev. 3.00 Sep.
2 Section 15 I C Bus Interface 2 (IIC2) Section 15 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 15.1 shows a block diagram of the I2C bus interface 2. Figure 15.2 shows an example of I/O pin connections to external circuits. 15.
2 Section 15 I C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmit/ receive control circuit Output control SCL ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT Output control SDA ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus
2 Section 15 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SDA in SCL SDA SDA out SCL in (Master) SCL SDA SCL out SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I2C bus interface 2. Table 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3 Register Descriptions The I2C bus interface 2 has the following registers. • • • • • • • • • I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) 15.3.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
2 Section 15 I C Bus Interface 2 (IIC2) Table 15.2 Transfer Rate Bit 3 Bit 1 Bit 0 CKS3 CKS2 Bit 2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz 0 0 0 φ/28 179 kHz 286 kHz 357 kHz 1 φ/40 125 kHz 200 kHz 250 kHz 0 φ/48 104 kHz 167 kHz 208 kHz 1 φ/64 78.1 kHz 125 kHz 156 kHz 0 φ/80 62.5 kHz 100 kHz 125 kHz 1 φ/100 50.0 kHz 80.0 kHz 100 kHz 0 1 1 0 1 1 0 0 1 1 0 1 0 φ/112 44.6 kHz 71.4 kHz 89.3 kHz 1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz 0 φ/56 89.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial format, this bit has no meaning.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. 2 1 Reserved This bit is always read as 1. 1 IICRST 0 R/W IIC Control Part Reset 2 This bit resets the control part except for I C registers.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 BCWP 1 R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 When 0 is written in NACKF after reading NACKF = 1 R/W Stop Condition Detection Flag [Setting conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a stop c
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave address is detected in slave receive mode • When the general call address is detected in slave receive mode.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 I2C Bus Format Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
2 Section 15 I C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 15.4.
2 Section 15 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
2 Section 15 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 15.7 Master Receive Mode Operation Timing (1) Rev. 3.00 Sep.
2 Section 15 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS ICDRR User processing Data n Data n-1 Data n Data n-1 [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 15.8 Master Receive Mode Operation Timing (2) 15.4.
2 Section 15 I C Bus Interface 2 (IIC2) Slave transmit mode Slave receive mode SCL (Master output) 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 15.10 Slave Transmit Mode Operation Timing (2) 15.4.
2 Section 15 I C Bus Interface 2 (IIC2) 4. The last byte data is read by reading ICDRR. SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR [2] Read ICDRR (dummy read) Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format: Figure 15.13 shows the clocked synchronous serial transfer format.
2 Section 15 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 SDA (Output) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 TRS TDRE Data 1 ICDRT Data 1 ICDRS User processing Data 2 [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS Data 3 Data 2 Data 3 [3] Write data to ICDRT [3] Write data to ICDRT Figure 15.14 Transmit Mode Operation Timing (3) Receive Operation: In receive mode, data is latched at the rise of the transfer clock.
2 Section 15 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 2 SDA (Input) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 MST TRS RDRF Data 2 Data 1 ICDRS ICDRR Data 3 Data 1 User processing [2] Set MST (when outputting the clock) Data 2 [3] Read ICDRR [3] Read ICDRR Figure 15.15 Receive Mode Operation Timing 15.4.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through the noise canceler before being latched internally. Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 15.17 to 15.20. Start [1] Test the status of the SCL and SDA lines. Initialize Read BBSY in ICCR2 No [2] Set master transmit mode. [1] BBSY=0 ? [3] Issue the start candition. Yes Set MST and TRS in ICCR1 to 1. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP.
2 Section 15 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Clear TRS in ICCR1 to 0 [1] [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* Clear TDRE in ICSR Clear ACKBT in ICIER to 0 [2] [4] Wait for 1 byte to be received Dummy-read ICDRR [3] [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No RDRF=1 ? [6] Read the receive data last. [4] [7] Set acknowledge of the final byte.
2 Section 15 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. Read TDRE in ICSR [3] No [2] Set transmit data for ICDRT (except for the last data). [6] Clear the TEND flag . TDRE=1 ? [7] Set slave receive mode. Yes [8] Dummy-read ICDRR to release the SCL line.
2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? No Read ICDRR Yes [8] Read the (last byte - 1) of receive data.
2 Section 15 I C Bus Interface 2 (IIC2) 15.5 Interrupts There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 15.3 shows the contents of each interrupt request. Table 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 15.21 shows the timing of the bit synchronous circuit and table 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.7 Usage Notes 15.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1.
Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.
Section 16 A/D Converter Internal data bus AVCC AN0 AN1 AN2 AN3 Analog multiplexer 10-bit D/A A D D R A A D D R B A D D R C A D D R D Bus interface Successive approximations register Module data bus A D C S R A D C R + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 16.
Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. Table 16.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply pin Analog input pin 0 AN0 Input Analog input pins Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input A/D external trigger input pin ADTRG Input 16.
Section 16 A/D Converter Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. ADDR is initialized to H'0000. Table 16.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel A/D Data Register to Be Stored Results of A/D Conversion AN0 ADDRA AN1 ADDRB AN2 ADDRC AN3 ADDRD 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Selects the A/D conversions time 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time. 2 CH2 0 R/W Channel Select 0 to 2 1 CH1 0 R/W Select analog input channels.
Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGE 0 R/W Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1.
Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.
Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D conversion time. As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time.
Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. CKS = 1 Typ. Max. Min. Typ. Max. A/D conversion start delay tD 6 — 9 4 — 5 Input sampling time tSPL — 31 — — 15 — A/D conversion time tCONV 131 — 134 69 — 70 Note: All values represent the number of states. 16.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 16.5).
Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev. 3.00 Sep.
Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. Figure 17.1 shows the block diagram of how BGR is allocated.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.1 Features • BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. Reduces power consumption when BGR is disabled by setting registers. • Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits φ OVF CK PSS R R RES Noise filter circuit Internal reset signal Q S CRES Power-on reset circuit Noise filter circuit External power supply Vcc Vreset VintU VintD ExtD LVDRES LVDINT Interrupt control circuit LVDSR Internal data bus LVDCR Ladder network ExtU VDDII Interrupt request VBGR [Legend] PSS: LVDCR: LVDSR: VBGR: ExtD: ExtU: VDDII: Prescaler S Low-voltage-detection control register Low-voltage-detection
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) 17.2.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Bit Bit Name Initial Value R/W Description 3 LVDSEL 0* R/W LVDR Detection Level Select 0: Reset detection voltage is 2.3 V (Typ.) 1: Reset detection voltage is 3.6 V (Typ.) When the falling or rising voltage detection interrupt is used, the reset detection voltage of 2.3 V (Typ.) should be used. When only a reset detection interrupt is used, reset detection voltage of 3.6 V (Typ.) should be used.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective given values. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1 and cannot be modified. 1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag [Setting condition] • When the power-supply voltage falls below Vint (D) (Typ.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.3 Operations 17.3.1 Power-On Reset Circuit Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and the entire chip retains the reset state.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits tPWON Vcc Vpor Vss RES Vss PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.3 Operational Timing of Power-On Reset Circuit 17.3.2 (1) Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detection) Circuit Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is enabled after a power-on reset is released.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.4 Operating Timing of LVDR Circuit (2) Low Voltage Detection Interrupt (LVDI) Circuit (When Internally Generated Voltage is used for Detection) Figure 17.5 shows the timing of the operation of the LVDI circuit.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits EEPROM and a transition to standby mode or subsleep mode must be made. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and rises above the Vint (U) (Typ. = 4.0 V) voltage, the LVDI circuit sets the LVDINT signal to 1.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits (3) Low Voltage Detection Interrupt (LVDI) Circuit (When Voltages Input via ExtU and ExtD Pins are used for Detection) Figure 17.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF and LVDUF bits in LVDSR must be cleared to 0 and the LVDDE or LVDUE bit in LVDCR must be set to 1.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits External power supply voltage ExtD input voltage (1) ExtU input voltage (2) Vexd (3) (4) Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 17.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins) Rev. 3.00 Sep.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits (4) Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits The low-voltage detection circuit is enabled after reset. To enable or disable the low-voltage detection circuit correctly, follow the procedure described below. Figure 17.7 shows the timing for the operation and release of the low-voltage detection circuit. 1. 2. 3.
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Rev. 3.00 Sep.
Section 18 Power Supply Circuit Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 18 Power Supply Circuit 18.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 18.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • • Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. 2.
Section 19 List of Registers 19.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Section 19 List of Registers Register Name Abbreviation Bit No Module Address Name Data Bus Access Width State Timer I/O control register 0 TIOR0 8 H'FF84 Timer W 8 Timer I/O control register 1 TIOR1 8 H'FF85 Timer W 8 Timer counter General register A TCNT GRA 16 16 H'FF86 H'FF88 Timer W Timer W 2 2 1 2 1 2 1 16* 16* General register B GRB 16 H'FF8A Timer W 16* 2 General register C GRC 16 H'FF8C Timer W 16*1 2 H'FF8E Timer W 1 16* 2 General register D GRD 16
Section 19 List of Registers Register Name Abbreviation Bit No Module Address Name Data Bus Access Width State Timer counter WD TCWD 8 H'FFC1 WDT*2 8 2 2 Timer mode register WD TMWD 8 H'FFC2 WDT* 8 2 Address break control register ABRKCR 8 H'FFC8 Address break 8 2 Address break status register ABRKSR 8 H'FFC9 Address break 8 2 Break address register H BARH 8 H'FFCA Address break 8 2 Break address register L BARL 8 H'FFCB Address break 8 2 Break data register H
Section 19 List of Registers Register Name Abbreviation Bit No Module Address Name Data Bus Access Width State Interrupt flag register 1 IRR1 8 H'FFF6 Interrupts 8 2 Interrupt flag register 2 IRR2 8 H'FFF7 Interrupts 8 2 Wake-up interrupt flag register IWPR 8 H'FFF8 Interrupts 8 2 Module standby control register 1 MSTCR1 8 H'FFF9 Power-down 8 2 Module standby control register 2 MSTCR2 8 H'FFFA Power-down 8 2 Notes: 1. Only word access can be used. 2.
Section 19 List of Registers 19.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name GRC GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9 GRC8 Timer W GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0 GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9 GRD8 GRD GRD7 GRD6 GRD5 GRD4 GRD3 GRD2 GRD1 GRD0 FLMCR1 — SWE ESU PSU EV PV E P FLMCR2 FLER — — — — — — — EBR1 — — EB5 EB4 EB3 EB2 EB1 EB0 FENR FLSHE — — — — — — — TCRV0 CMIEB CMIEA OVIE
Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 ABRKSR ABIF ABIE — — — — — — BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0 BDRH BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0 BDRL BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 PUCR1 PUCR17 — — PUCR14 — PUCR5 — — PUCR55 — — — — — PDR1 P17 — — —
Section 19 List of Registers 19.
Section 19 List of Registers Register Name Reset Active Sleep Subsleep Standby Module TCSRV Initialized — — Initialized Initialized Timer V TCORA Initialized — — Initialized Initialized TCORB Initialized — — Initialized Initialized TCNTV Initialized — — Initialized Initialized TCRV1 Initialized — — Initialized Initialized SMR Initialized — — Initialized Initialized BRR Initialized — — Initialized Initialized SCR3 Initialized — — Initialized Initialized
Section 19 List of Registers Register Name Reset Active Sleep Subsleep Standby Module PDRC Initialized — — — — I/O port PMR1 Initialized — — — — PMR5 Initialized — — — — PCR1 Initialized — — — — PCR2 Initialized — — — — PCR5 Initialized — — — — PCR7 Initialized — — — — PCR8 Initialized — — — — PCRC Initialized — — — — SYSCR1 Initialized — — — — SYSCR2 Initialized — — — — IEGR1 Initialized — — — — IEGR2 Initialized — — — —
Section 19 List of Registers Rev. 3.00 Sep.
Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage VIN Ports other than port B Port B –0.3 to VCC +0.3 V –0.3 to AVCC +0.
Section 20 Electrical Characteristics 20.2 Electrical Characteristics (F-ZTATTM Version) 20.2.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and external oscillation frequency range φosc(MHz) 12.0 2.0 3.0 5.5 Vcc(V) AVcc = 3.0 to 5.5 V • Active mode • Sleep mode 2. Power supply voltage and operating frequency range φosc(MHz) φ(kHz) 12.0 1500 2.0 31.25 3.0 5.5 AVcc = 3.0 to 5.5 V • Active mode • Sleep mode (When MA2 = 0 in SYSCR2) Rev. 3.00 Sep.
Section 20 Electrical Characteristics 3. Analog power supply voltage and A/D converter accuracy guarantee range φosc(MHz) 12.0 2.0 3.0 5.5 AVcc(V) Vcc = 3.0 to 5.5 V • Active mode • Sleep mode Rev. 3.00 Sep.
Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated. Item Symbol Input high VIH voltage Applicable Pins Test Condition RES, NMI, WKP5, VCC = 4.0 V to 5.5 V IRQ0, IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, VCC = 4.0 V to 5.5 V P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 PB3 to PB0 AVCC = 4.0 V to 5.
Section 20 Electrical Characteristics Item Symbol Output high voltage VOH Applicable Pins P17, P14, P22 to P20, P55, P76 to P74, P84 to P80, PC1, PC0 P56, P57 Values Test Condition Min. VCC = 4.0 V to 5.5 V Typ. Max. Unit VCC – 1.0 — — V –IOH = 0.1 mA VCC – 0.5 — — V VCC = 4.0 V to 5.5 V VCC – 2.5 — — V VCC – 2.2 — — V — — 0.6 V IOL = 0.4 mA — — 0.4 V VCC = 4.0 V to 5.5 V — — 1.5 V — — 1.0 V — — 0.4 V IOL = 0.4 mA — — 0.4 V VCC = 4.0 V to 5.5 V — — 0.
Section 20 Electrical Characteristics Item Symbol Applicable Pins Pull-up MOS current –Ip P17, P14, P55 Input capacitance Cin Test Condition Values Min. Typ. Max. Unit VCC = 5.0 V, VIN = 0.0 V 50.0 — 300.0 µA VCC = 3.0 V, VIN = 0.0 V — 60.0 — µA All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF Active IOPE1 mode current consumption VCC Active mode 1 VCC = 5.0 V, fOSC = 12 MHz — 12.0 18.0 mA * Active mode 1 VCC = 3.
Section 20 Electrical Characteristics Item Symbol RAM data VRAM retaining voltage Note: * Applicable Pins Test Condition VCC Values Min. Typ. Max. Unit 2.0 — — V Notes Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated. Item Application Symbol Pins Allowable output low IOL current (per pin) Allowable output low ∑IOL current (total) Allowable output high I –IOH I current (per pin) Values Typ. Max. Unit VCC = 4.0 V to 5.5 V — Output pins except P84 to P80, SCL, and SDA — 2.0 mA P84 to P80 — — 20.0 mA Output pins except P84 to P80, SCL, and SDA — — 0.
Section 20 Electrical Characteristics 20.2.3 AC Characteristics Table 20.3 AC Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Applicable Symbol Pins Item System clock fOSC oscillation frequency System clock (φ) cycle tcyc time OSC1, OSC2 Instruction cycle time Test Condition Values Reference Min. Typ. Max. Unit Figure 2.0 — 12.0 MHz 1 — 64 tOSC — — 32.0 µs 2 — — tcyc 1 * Figure 20.
Section 20 Electrical Characteristics Item Applicable Symbol Pins On-chip oscillator fRC 2 oscillation frequency * Test Condition VCC = 5.0 V Ta = 25°C FSEL = 0, VCLSEL = 0 Values Reference Typ. Max. Unit Figure Min. 3 7.92* 8.0 VCC = 4.0 V to 5.5 V 7.76 FSEL = 0, VCLSEL = 0 3 VCC = 4.0 V to 5.5 V 9.6* FSEL = 1, VCLSEL = 0 8.0 3 8.08* MHz 8.24 MHz 3 10.0 10.4* MHz Notes: 1. Determined by MA2 to MA0 in system control register 2 (SYSCR2). 2.
Section 20 Electrical Characteristics Table 20.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Applicable Test Symbol Pins Condition Min. SCL input cycle time tSCL SCL input high pulse width tSCLH SCL input low pulse width tSCLL Values Max.
Section 20 Electrical Characteristics Table 20.5 Serial Interface (SCI3) Timing VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Input clock cycle Asynchronous Symbol Applicable Pins tscyc SCK3 Clocked synchronous Test Condition Values Min. Typ. Max. Unit 4 — — tcyc 6 — — tcyc Input clock pulse width tSCKW SCK3 0.4 — 0.
Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Values Item Symbol Applicable Test Pins Condition Analog power supply voltage AVCC AVCC 3.0 VCC 5.5 Analog input voltage AVIN AN3 to AN0 VSS – 0.3 — AVCC + V 0.3 Analog power supply current AIOPE AVCC — 2.0 mA AISTOP1 AVCC — 50 — µA * Reference value AISTOP2 AVCC — — 5.
Section 20 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min. AVCC = 4.0 V 134 to 5.5 V Typ. Max. Unit — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Notes Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 20 Electrical Characteristics 20.2.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Min. Typ. Max. Unit Power-supply falling detection voltage Vint(D) LVDSEL = 0 3.3 3.7 4.3 V Power-supply rising detection voltage Vint(U) LVDSEL = 0 3.6 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 2.0 2.3 2.
Section 20 Electrical Characteristics 20.2.8 Power-On Reset Characteristics Table 20.10 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ. Max. Unit Pull-up resistance of RES pin RRES 100 150 — kΩ Power-on reset start voltage* Vpor — — 100 mV Note: * The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely.
Section 20 Electrical Characteristics 20.2.9 Flash Memory Characteristics Table 20.11 Flash Memory Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Test Condition Values Item Symbol Min. Typ. Max.
Section 20 Electrical Characteristics Min. Typ. Max.
Section 20 Electrical Characteristics 20.3 Electrical Characteristics (Masked ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and external oscillation frequency range φosc(MHz) 12.0 2.0 2.7 5.5 Vcc(V) AVcc = 2.7 to 5.5 V • Active mode • Sleep mode 2. Power supply voltage and operating frequency range φosc(MHz) φ(kHz) 12.0 1500 2.0 31.25 2.7 5.5 Vcc(V) AVcc = 2.7 to 5.5 V • Active mode • Sleep mode (When MA2 = 0 in SYSCR2) 2.7 5.5 Vcc(V) AVcc = 2.7 to 5.
Section 20 Electrical Characteristics 3. Analog power supply voltage and A/D converter accuracy guarantee range φosc(MHz) 12.0 2.0 2.7 Vcc = 2.7 to 5.5 V • Active mode • Sleep mode Rev. 3.00 Sep. 14, 2006 Page 332 of 408 REJ09B0105-0300 5.
Section 20 Electrical Characteristics 20.3.2 DC Characteristics Table 20.12 DC Characteristics (1) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated. Item Applicable Symbol Pins Input high VIH voltage Test Condition RES, NMI, WKP5, VCC = 4.0 V to 5.5 V IRQ0, IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, VCC = 4.0 V to 5.5 V P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 PB3 to PB0 AVCC = 4.0 V to 5.
Section 20 Electrical Characteristics Item Symbol Output high voltage VOH Applicable Pins P17, P14, P22 to P20, P55, P76 to P74, P84 to P80, PC1, PC0 P56, P57 Test Condition Min. Typ. Max. Unit VCC – 1.0 — — V –IOH = 0.1 mA VCC – 0.5 — — V VCC = 4.0 V to 5.5 V VCC – 2.5 — — V VCC – 2.2 — — V — — 0.6 V IOL = 0.4 mA — — 0.4 V VCC = 4.0 V to 5.5 V — — 1.5 V — — 1.0 V — — 0.4 V IOL = 0.4 mA — — 0.4 V VCC = 4.0 V to 5.5 V — — 0.6 V VCC = 4.0 V to 5.
Section 20 Electrical Characteristics Item Symbol Applicable Pins Pull-up MOS current –Ip P17, P14, P55 Input capacitance Cin Test Condition Values Min. Typ. VCC = 5.0 V, VIN = 0.0 V 50.0 — 300.0 µA VCC = 2.7 V, VIN = 0.0 V — 60.0 — µA All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF Active IOPE1 mode current consumption VCC Active mode 1 VCC = 5.0 V, fOSC = 12 MHz — 12.0 18.0 mA * Active mode 1 VCC = 2.7 V, fOSC = 12 MHz — 9.
Section 20 Electrical Characteristics Item Symbol RAM data VRAM retaining voltage Note: * Applicable Pins Test Condition VCC Values Min. Typ. 2.0 — Max. — Unit Notes V Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 20 Electrical Characteristics Table 20.12 DC Characteristics (2) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated. Item Symbol Allowable output low IOL current (per pin) Test Condition Output pins except P84 to P80, SCL, and SDA VCC = 4.0 V to 5.5 V — Allowable output high I –IOH I current (per pin) Allowable output high I –∑IOH I current (total) Min. Typ. Max. Unit — 2.0 mA P84 to P80 — — 20.
Section 20 Electrical Characteristics 20.3.3 AC Characteristics Table 20.13 AC Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Symbol Applicable Pins System clock oscillation frequency System clock (φ) cycle time fOSC OSC1, OSC2 Test Condition tcyc Instruction cycle time Values Min. Typ. Max. Unit 2.0 — 12.0 MHz 1 — 64 tOSC — — 32.0 µs 2 — — tcyc Reference Figure * Figure 20.1 trc OSC1, OSC2 — — 10.
Section 20 Electrical Characteristics Item Symbol Input pin low width tIL On-chip oscillator oscillation frequency Notes: * fRC Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure 2 — — tcyc Figure 20.3 VCC = 4.0 V to 5.5 V FSEL = 0, VCLSEL = 0 7.6 8.0 8.4 MHz VCC = 4.0 V to 5.5 V FSEL = 1, VCLSEL = 0 9.4 10.0 10.6 MHz IRQ0, IRQ3, WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD Determined by MA2 to MA0 in system control register 2 (SYSCR2). Rev. 3.
Section 20 Electrical Characteristics Table 20.14 I2C Bus Interface Timing VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Applicable Pins Test Condition Min. Values Reference Max.
Section 20 Electrical Characteristics Table 20.15 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Input clock cycle Asynchronous Symbol Applicable Pins tscyc SCK3 Clocked synchronous Test Condition Values Min. Typ. Max. Unit 4 — — tcyc 6 — — tcyc Input clock pulse width tSCKW SCK3 0.4 — 0.
Section 20 Electrical Characteristics 20.3.4 A/D Converter Characteristics Table 20.16 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Applicable Symbol Pins Test Condition Values Min. Typ. Max. Unit Notes VCC V * Analog power supply voltage AVCC AVCC 2.7 Analog input voltage AVIN AN3 to AN0 VSS – 0.3 — AVCC + 0.3 V Analog power supply current AIOPE AVCC — — 2.0 mA AVCC = 5.0 V 5.
Section 20 Electrical Characteristics Item Symbol Applicable Test Pins Condition Conversion time (single mode) AVCC = 4.0 V to 5.5 V Values Min. Typ. Max. Unit 134 — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Notes Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 20 Electrical Characteristics 20.3.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.18 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Typ. Max. Unit Power-supply falling detection voltage Vint(D) LVDSEL = 0 3.3 3.7 4.3 V Power-supply rising detection voltage Vint(U) LVDSEL = 0 3.6 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 2.0 2.3 2.
Section 20 Electrical Characteristics 20.3.8 Power-On Reset Characteristics Table 20.20 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ. Max. Unit Pull-up resistance of RES pin RRES 100 150 — kΩ Power-on reset start voltage* Vpor — — 100 mV Note: * The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely.
Section 20 Electrical Characteristics 20.4 Operation Timing tOSC VIH VIL OSC1 tCPH tCPL tCPr tCPf Figure 20.1 System Clock Input Timing Vcc Vcc × 0.7 OSC1 tREL RES VIL VIL tREL Figure 20.2 RES Low Width Timing IRQ0, IRQ3 WKP5, NMI ADTRG FTCI, FTIOA VIH VIL FTIOB, FTIOC tIL tIH FTIOD TMCIV, TMRIV TRGV Figure 20.3 Input Timing Rev. 3.00 Sep.
Section 20 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSr tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop comdition Sr: Retransmission start condition Figure 20.4 I2C Bus Interface Input/Output Timing tSCKW SCK3 tscyc Figure 20.5 SCK3 Input Clock Timing Rev. 3.00 Sep.
Section 20 Electrical Characteristics t scyc VIH or VOH * VIL or VOL * SCK3 t TXD VOH* TXD (transmit data) VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL= 0.8 V Load conditions are shown in figure 20.7. Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode 20.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 20.7 Output Load Circuit Rev. 3.00 Sep.
Appendix Appendix A Instruction Set A.
Appendix Symbol Description ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Symbol Description ↔ • Condition Code Notation Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 3.00 Sep.
Appendix Table A.1 Instruction Set • Data transfer instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
Appendix • Arithmetic instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
Appendix No. of States*1 L 0–ERd32 → ERd32 2 — EXTU EXTU.W Rd W 0 → ( of Rd16) 2 — — 0 L 0 → ( of ERd32) 2 — — 0 W ( of Rd16) → ( of Rd16) 2 — — L ( of ERd32) → ( of ERd32) 2 — — Advanced NEG.L ERd Normal ↔ ↔ ↔ — ↔ ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ C ↔ ↔ ↔ ↔ W 0–Rd16 → Rd16 EXTS.L ERd V 2 0 — 2 ↔ NEG.W Rd EXTS EXTS.W Rd Z 0 — 2 ↔ — 0 — 2 ↔ H 2 EXTU.L ERd N ↔ I B 0–Rd8 → Rd8 NEG NEG.
Appendix • Logic instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix • Shift instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix • Bit manipulation instructions B BSET #xx:3, @aa:8 B BSET Rn, Rd B BSET Rn, @ERd B BSET Rn, @aa:8 B B BCLR #xx:3, @ERd B BCLR #xx:3, @aa:8 B BCLR Rn, Rd B BCLR Rn, @ERd B BCLR Rn, @aa:8 B BNOT BNOT #xx:3, Rd B BNOT #xx:3, @ERd B BNOT #xx:3, @aa:8 B BNOT Rn, Rd B BNOT Rn, @ERd B BNOT Rn, @aa:8 B BTST BTST #xx:3, Rd B BTST #xx:3, @ERd B BTST #xx:3, @aa:8 B BTST Rn, Rd B BTST Rn, @ERd B BTST Rn, @aa:8 B BLD #xx:3, Rd B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd B BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BIST BST #xx:3, @aa:8 B BST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BIAND BAND #xx:3, @aa:8 B BOR BIAND #xx:3, Rd B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix • Branching instructions Bcc Condition Code — 2 BRA d:16 (BT d:16) — 4 BRN d:8 (BF d:8) — 2 BRN d:16 (BF d:16) — 4 BHI d:8 — 2 BHI d:16 — 4 BLS d:8 — 2 BLS d:16 — 4 BCC d:8 (BHS d:8) — 2 BCC d:16 (BHS d:16) — 4 BCS d:8 (BLO d:8) — 2 BCS d:16 (BLO d:16) — 4 BNE d:8 — 2 BNE d:16 — 4 BEQ d:8 — 2 BEQ d:16 — 4 BVC d:8 — 2 BVC d:16 — 4 BVS d:8 — 2 BVS d:16 — 4 BPL d:8 — 2 BPL d:16 — 4 BMI d:8 — 2 BMI d:16 — 4 BGE d:8 — 2 BGE d:
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
Appendix • System control instructions No.
Appendix • Block transfer instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
REJ09B0105-0300 Rev. 3.00 Sep. 14, 2006 Page 364 of 408 MULXU 5 STC LDC 3 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST TRAPA BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A-2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.B XORC 5 ADD BNOT DIVXU BRN OR.
MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 ADD ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table
REJ09B0105-0300 Rev. 3.00 Sep. 14, 2006 Page 366 of 408 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 19.1, Register Addresses (Address Order). Rev. 3.00 Sep.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 Branch Stack Addr. Read Operation J K Byte Data Access L AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
Appendix Instruction Mnemonic Instruction Fetch I Bcc BLT d:8 2 BGT d:8 2 BLE d:8 2 BRA d:16(BT d:16) 2 2 BRN d:16(BF d:16) 2 2 BHI d:16 2 2 BLS d:16 2 2 BCC d:16(BHS d:16) 2 2 BCS d:16(BLO d:16) 2 2 BNE d:16 2 2 BEQ d:16 2 2 BVC d:16 2 2 BVS d:16 2 2 BPL d:16 2 2 BMI d:16 2 2 BGE d:16 2 2 BLT d:16 2 2 BGT d:16 2 2 BLE d:16 2 2 BCLR #xx:3, Rd 1 BCLR #xx:3, @ERd 2 2 BCLR #xx:3, @aa:8 2 2 BCLR Rn, Rd 1 BCLR Rn, @ERd 2 2 BCLR Rn, @aa:8 2
Appendix Instruction Mnemonic Instruction Fetch I BIOR BIOR #xx:8, Rd 1 BIOR #xx:8, @ERd 2 1 BIOR #xx:8, @aa:8 2 1 BIST #xx:3, Rd 1 BIST #xx:3, @ERd 2 2 BIST #xx:3, @aa:8 2 2 BIXOR #xx:3, Rd 1 BIXOR #xx:3, @ERd 2 1 BIXOR #xx:3, @aa:8 2 1 BIST BIXOR BLD BNOT BOR BSET BSR BST Branch Stack Addr.
Appendix Instruction Mnemonic Instruction Fetch I BTST BXOR CMP BTST #xx:3, Rd 1 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.L ERs, ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DUVXS DIVXU EEPMOV EXTS EXTU Byte Data Access L BTST #xx:3, @ERd CMP.B Rs, Rd DEC Branch Stack Addr.
Appendix Instruction Mnemonic Instruction Fetch I INC JMP JSR LDC MOV Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M INC.B Rd 1 INC.W #1/2, Rd 1 INC.L #1/2, ERd 1 JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 2 JSR @ERn 2 JSR @aa:24 2 JSR @@aa:8 2 LDC #xx:8, CCR 1 LDC Rs, CCR 1 LDC@ERs, CCR 2 1 LDC@(d:16, ERs), CCR 3 1 LDC@(d:24,ERs), CCR 5 1 LDC@ERs+, CCR 2 1 LDC@aa:16, CCR 3 1 LDC@aa:24, CCR 4 1 MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.
Appendix Instruction Mnemonic Instruction Fetch I MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.
Appendix Instruction Mnemonic Instruction Fetch I MULXS MULXU NEG 12 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP 1 1 NOT.W Rd 1 NOT.L ERd 1 PUSH ROTL ROTR ROTXL Internal Operation N 2 NOT.B Rd POP Word Data Access M MULXS.B Rs, Rd NOT ORC Byte Data Access L MULXS.W Rs, ERd NOP OR Branch Stack Addr. Read Operation J K OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Mnemonic Instruction Fetch I ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAR SHLL SHLR SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
Appendix Instruction Mnemonic Instruction Fetch I SUBX TRAPA XOR XORC SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 TRAPA #xx:2 2 XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 Branch Stack Addr. Read Operation J K 1 2 Byte Data Access L Word Data Access M Internal Operation N 4 Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 — — — — — — — WL — BWL BWL — @(d:16.PC) — — — @aa:24 — — — B @aa:16 — — — @aa:8 @ERn+/@ERn @(d:24.ERn) @ERn BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, Rn Instructions #xx Functions @(d:16.
Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14) Rev. 3.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TXD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 2 Block Diagram (P22) Rev. 3.00 Sep.
Appendix SBY Internal data bus PDR PCR SCI3 RE RXD [Legend] PDR: Port data register PCR: Port control register Figure B.4 Port 2 Block Diagram (P21) Rev. 3.00 Sep.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P20) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: PCR: Portdata register Portcontrol register Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.7 Port 5 Block Diagram (P55) Rev. 3.00 Sep.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.8 Port 5 Block Diagram (P76) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.9 Port 7 Block Diagram (P75) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.10 Port 7 Block Diagram (P74) Rev. 3.00 Sep.
Appendix Internal data bus SBY Timer W Output control signal A to D PDR PCR FTIOA to D [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.11 Port 8 Block Diagram (P84 to P81) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer W FTCI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.12 Port 8 Block Diagram (P80) Rev. 3.00 Sep.
Appendix Internal data bus A/D converter CH3 to CH0 SCAN VIN DEC Low voltage detection circuit VDDII ExtD, ExtU [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.13 Port B Block Diagram (PB3, PB2) Internal data bus A/D converter SCAN CH3 to CH0 DEC VIN Figure B.14 Port B Block Diagram (PB1, PB0) Rev. 3.00 Sep.
Appendix SBY Internal data bus CPG PDR φ PCR PMRC1 PMRC0 XTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.15 Port C Block Diagram (PC1) Rev. 3.00 Sep.
Appendix SBY Internal data bus PDR PCR CPG PMRC0 EXTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.16 Port C Block Diagram (PC0) B.
Appendix Appendix C Product Code Lineup Product Type Product Code Model Marking Package Code H8/36912 Flash memory version HD64F36912G HD64F36912GFH LQFP-32 (FP-32A) HD64F36912GTP SOP-32 (FP-32D) Masked ROM version HD64336912G H8/36911 Masked ROM version HD64336911G H8/36902 Flash memory version HD64F36902G Masked ROM version HD64336902G H8/36901 Masked ROM version HD64336901G H8/36900 Masked ROM version HD64336900G HD64F36912GP SDIP-32 (32P4B) HD64336912G (***) FH LQFP-32 (FP-32A)
Appendix Appendix D Package Dimensions The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority. Unit: mm 20.45 20.95 Max 17 11.30 32 1 1.27 *0.40 ± 0.08 0.38 ± 0.06 0.10 0.15 M *Dimension including the plating thickness Base material dimension 0.12 0.15 +– 0.10 0.20 ± 0.04 1.00 Max *0.22 ± 0.05 3.00 Max 16 14.14 ± 0.30 1.42 0˚ – 8˚ 0.80 ± 0.20 Package Code JEDEC JEITA Mass (reference value) Figure D.1 FP-32D Package Dimensions Rev. 3.00 Sep.
Appendix Unit: mm 9.0 ± 0.2 7 17 25 16 32 9 1 0. 8 24 8 0.70 0.5 ± 0.1 0.10 0.15 ± 0. 04 *0.17 ± 0. 05 1.40 1. 0 1.70Max 0 .20 M Package Code *Dimension including the plating thickness Base material dimension 0 ~ 10˚ 0.10 ± 0. 07 * 0.35 ± 0.05 0.37 ± 0.05 JEDEC JEITA Mass (reference value) FP-32A FP-32AV — — 0.2 g Figure D.2 FP-32A Package Dimension Rev. 3.00 Sep.
Appendix 17 1 16 θ E 32 e1 C Unit: mm L A1 A A2 D e b1 b b2 SEATING PLANE Symbol A A1 A2 b b1 b2 c D E e e1 L θ Dimension in Millmeters Nom Min Max 5.08 − − − − 0.51 − 3.8 − 0.55 0.45 0.35 1.3 1.0 0.9 1.03 0.73 0.63 0.34 0.27 0.22 28.2 28.0 27.8 9.05 8.9 8.75 − 1.778 − − 10.16 − − − 3.0 15˚ − 0˚ Package Code JEDEC JEITA Mass (reference value) Figure D.3 32P4B Package Dimension Rev. 3.00 Sep. 14, 2006 Page 398 of 408 REJ09B0105-0300 32P4B — — 2.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface When using an on-chip emulator (E7, E8) for H8/36912, H8/36902 program development and debugging, the following restrictions must be noted. 1.The NMI pin is reserved for the E7 or E8, and cannot be used. 2.Area H'2000 to H'2FFF is used by the E7 or E8, and is not available to the user. 3.Area H'F980 to H'FD7F must on no account be accessed. 4.
(OSC1) (OSC2) Figure 1.2 Internal Block Diagram of H8/36902 Group E10T_0* E10T_1* E10T_2* CPU H8/300H On-chip oscillator Address bus System clock generator bus (upper) NMI TEST RES VCL Figure 1.1 Internal Block 3, 4 Diagram of H8/36912 Group VCC Page Revision (See Manual for Details) VSS Item Data bus (lower) Port C PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 AVCC PC0/OSC1 PC1/OSC2/CLKOUT Port B Note: * Can also be used for the E7 or E8 emulator.
Item Page Revision (See Manual for Details) Figure 2.1 Memory Map (2) 13 H8/36911 H8/36901 (Masked ROM version (under planning)) H'0000 H'0045 H'0046 Table 3.1 Exception Sources 48 and Vector Address H8/36900 (Masked ROM version (under planning)) H'0000 H'0045 H'0046 Interrupt vector Interrupt vector Relative Module Exception Sources IIC2* IIC_2 transmit data empty IIC_2 transmit end IIC_2 receive error Timer B1* Timer B1 overflow Note: * Available for the H8/36912 Group only. Figure 5.
Item Page Revision (See Manual for Details) 5.2.3 RC Trimming Data Register (RCTRMDR) 73 5.2.4 Clock Control/Status Register (CKCSR) 74 Figure 5.5 Timing Chart of 78 Switching On-chip Oscillator Clock to External Clock Table 5.1 Crystal Resonator 82 Parameters Bit Bit Name Description 7 TRMD7 Trimming Data 6 TRMD6 5 TRMD5 4 TRMD4 In the flash memory version, the trimming data is loaded from the flash memory to this register right after a reset.
Item Page Revision (See Manual for Details) 13.2.1 Timer Control/Status Register WD (TCSRWD) 192 Bit Bit Name Description 4 TCSRWE Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 14.8.2 Mark State and Break 236 Sending 15.3.
Item Page Revision (See Manual for Details) Table 20.13 AC Characteristics 339 Symbol Min. Typ. Max. On-chip oscillator oscillation frequency fRC 7.6 8.0 8.4 9.4 10.0 10.
Index A A/D converter ......................................... 273 A/D conversion time........................... 280 External trigger input.......................... 281 Sample-and-hold circuit...................... 280 Scan mode........................................... 279 Single mode ........................................ 279 Acknowledge .......................................... 255 Address break ........................................... 63 Addressing modes Absolute address.......................
Shift Instructions .................................. 25 System control instructions................... 29 Internal power supply step-down circuit...................................................... 299 Interrupt Internal interrupts ................................. 56 Interrupt response time ......................... 59 IRQ3 to IRQ0 interrupts ....................... 55 NMI interrupt........................................ 55 WKP5 to WKP0 interrupts ...................
ICMR.......................... 246, 302, 306, 309 ICSR ........................... 250, 302, 306, 309 IEGR1........................... 49, 304, 308, 311 IEGR2........................... 50, 304, 308, 311 IENR1........................... 50, 304, 308, 311 IRR1 ............................. 52, 305, 308, 311 IWPR ............................ 53, 305, 308, 311 LVDCR....................... 288, 302, 306, 309 LVDSR ....................... 290, 302, 306, 309 MSTCR1....................... 89, 305, 308, 311 MSTCR2.
T Timer B1................................................. 139 Auto-reload timer operation ............... 142 Interval timer operation ...................... 142 Timer V .................................................. 145 Timer W ................................................. 159 Transfer Rate .......................................... 244 Rev. 3.00 Sep. 14, 2006 Page 408 of 408 REJ09B0105-0300 V Vector address........................................... 47 W Watchdog timer........................
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36912 Group, H8/36902 Group Publication Date: Rev.1.00, Nov. 07, 2003 Rev.3.00, Sep. 14, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/36912 Group, H8/36902 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0105-0300
