Datasheet

Section 5 Clock Pulse Generators
Rev. 3.00 Sep. 14, 2006 Page 78 of 408
REJ09B0105-0300
5.3.2 Clock Change Timing
The timing for changing clocks are shown in figures 5.5 and 5.6.
[Legend]
φOSC: External clock
φRC: On-chip oscillator clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
Wait for external
oscillation settling
φ halt*
External clock operation
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the first
rising edge of the φ
OSC
clock after six clock cycles of the φ
RC
clock have elapsed.
φOSC
Nwait
φRC
PHISTOP
(Internal signal)
φ
OSCSEL
CKSTA
On-chip oscillator clock operation
Figure 5.5 Timing Chart of Switching On-chip Oscillator Clock to External Clock