Datasheet

Section 5 Clock Pulse Generators
Rev. 3.00 Sep. 14, 2006 Page 79 of 408
REJ09B0105-0300
[Legend]
φOSC: External clock
φRC: On-chip oscillator clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
CKSWIF: Bit 2 in CKCSR
Wait for external
oscillation settling
φ halt*
On-chip oscillator
clock operation
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φ
RC
clock.
φOSC
φRC
PHISTOP
(Internal signal)
φ
OSCSEL
CKSTA
External clock operation
Nwait
CKSWIF
Figure 5.6 Timing Chart to Switch External Clock to On-chip Oscillator Clock