Datasheet

Section 6 Power-Down Modes
Rev. 3.00 Sep. 14, 2006 Page 86 of 408
REJ09B0105-0300
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit Bit Name
Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
Specifies the operating mode to be entered after
executing the SLEEP instruction.
0: Shifts to sleep mode.
1: Shifts to standby mode.
For details, see table 6.2.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
These bits set the wait time from when the system clock
oscillator starts functioning until the clock is supplied, in
shifting from standby mode, to active mode or sleep
mode. During the wait time, this LSI automatically selects
the on-chip oscillator clock as its system clock and counts
the number of wait states. Select a wait time of 6.5 ms
(oscillation stabilization time) or longer, depending on the
operating frequency. Table 6.1 shows the relationship
between the STS2 to STS0 values and the wait time.
When using an external clock, set the wait time to be
100 µs or longer in the F-ZTAT version. In the masked
ROM version, the minimum value (STS2 = STS1 = STS0
= 1) is recommended.
These bits also set the wait states for external oscillation
stabilization when system clock is switched from the on-
chip oscillator clock to the external clock by user
software.
The relationship between Nwait (number of wait states for
oscillation stabilization) and Nstby (number of wait states
for recovering to the standby mode) is as follows.
Nstby ≤ Nwait ≤ 2 × Nstby
3 to 0  All 0  Reserved
These bits are always read as 0.