Datasheet

Section 6 Power-Down Modes
Rev. 3.00 Sep. 14, 2006 Page 88 of 408
REJ09B0105-0300
6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit Bit Name
Initial
Value R/W Description
7 SMSEL 0 R/W Sleep Mode Selection
This bit specifies the mode to be entered after executing
the SLEEP instruction, as well as the SSBY bit in
SYSCR1. For details, see table 6.2.
6  0  Reserved
This bit is always read as 0.
5 DTON 0 R/W Direct Transfer on Flag
This bit specifies the mode to be entered after executing
the SLEEP instruction, as well as the SSBY bit in
SYSCR1. For details, see table 6.2.
4
3
2
MA2
MA1
MA0
0
0
0
R/W
R/W
R/W
Active Mode Clock Select 2 to 0
These bits select the operating clock frequency in active
and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φ
100: φ /8
101: φ/16
110: φ/32
111: φ/64
1, 0  All 0  Reserved
These bits are always read as 0.
[Legend]
X: Don't care