Datasheet

Section 6 Power-Down Modes

Rev. 3.00 Sep. 14, 2006 Page 94 of 408

REJ09B0105-0300

6.2.3 Subsleep Mode

In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip

peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of

CPU registers, the on-chip RAM, and some on-chip peripheral module registers are retained. The

I/O ports keep the same states as before the transition.

Subsleep mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator

starts functioning. The external oscillator also starts functioning when used. After the time set by

the STS2 to STS0 bits in SYSCR1 has elapsed, subsleep mode is cleared and the CPU starts

interrupt exception handling. Subsleep mode is not cleared if the I bit in the condition code

When the RES pin is driven low in subsleep mode, the on-chip oscillator starts functioning. The

system clock is supplied to the entire chip as soon as the on-chip oscillator starts functioning. The

RES pin must be kept low for the rated period. On driving the RES pin high, after the oscillation

stabilization time set by the power-on reset circuit has elapsed, the internal reset signal is cleared

and the CPU starts reset exception handling.

6.3 Operating Frequency in Active Mode

Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in

SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction

execution.

6.4 Direct Transition

The CPU can execute programs in active mode. The operating frequency can be changed by

making a transition directly from active mode to active mode. A direct transition can be made by

executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. If the direct transition

interrupt is disabled by the interrupt enable register 1, a transition is made instead to sleep mode or

subsleep mode. Note that if a direct transition is attempted while the I bit in condition code

be cleared by means of an interrupt.