Datasheet

Section 7 ROM
Rev. 3.00 Sep. 14, 2006 Page 108 of 408
REJ09B0105-0300
START
End of programming
Notes: 1. The RTS instruction must not be used during the following (1) and (2) periods.
(1) A period between 64-byte data programming to flash memory and the P bit clearing
(2) A period between dummy writing of H'FF to a verify address and verify data reading
2. When WDT is in use, disable it once.
Set SWE bit in FLMCR1
Write pulse application subroutine
Wait 1 µs
Apply Write Pulse
* 1
End Sub
Set PSU bit in FLMCR1
WDT enable
Disable WDT
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = Programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
n = 1
m= 0
No
No
No Yes
Yes
Yes
Yes
Wait 4 µs
Wait 2 µs
Wait 2 µs
Apply Write pulse
Set PV bit in FLMCR1
Set block start address as
verify address
H'FF dummy write to verify address
Read verify data
Verify data =
Write data?
Reprogram data computation
Additional-programming data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
m = 0 ?
Increment address
Programming failure
No
Clear SWE bit in FLMCR1
Wait 100 µs
No
Yes
n ≤ 6?
No
Yes
n ≤ 6 ?
Wait 100
µs
n ≤ 1000 ?
n ← n + 1
Write 64-byte data in RAM reprogram
data area consecutively to flash memory
Store 64-byte program data in program
data area and reprogram data area
Apply Write Pulse
Sub-Routine-Call
64-byte
data verification completed?
Successively write 64-byte data from additional-
programming data area in RAM to flash memory
* 1
Disable WDT
* 2
Figure 7.3 Program/Program-Verify Flowchart