Datasheet

Section 7 ROM
Rev. 3.00 Sep. 14, 2006 Page 111 of 408
REJ09B0105-0300
Erase start
Set EBR1
Enable WDT
Wait 1 µs
Wait 100 µs
SWE bit ← 1
n ← 1
ESU bit ← 1
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
Wait 10 µs
Disable WDT
Read verify data
Increment address
Verify data = all 1s ?
Last address of block ?
All erase block erased ?
Set block start address as verify address
H'FF dummy write to verify address
Wait 20 µs
Wait 2 µs
EV bit ← 1
Wait 100 µs
End of erasing
Notes: 1. The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
2. When WDT is in use, disable it once.
SWE bit ← 0
Wait 4 µs
EV bit ← 0
n ≤100 ?
Wait 100 µs
Erase failure
SWE bit ← 0
Wait 4µs
EV bit ← 0
n ← n + 1
Ye s
No
Ye s
Ye s
Ye s
Ye s
No
No
No
*1
*2
Disable WDT
Figure 7.4 Erase/Erase-Verify Flowchart