Datasheet

Section 9 I/O Ports
Rev. 3.00 Sep. 14, 2006 Page 126 of 408
REJ09B0105-0300
9.3.3 Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
5
P57
P56
P55
0
0
0
R/W
R/W
R/W
These bits store output data for port 5 pins.
If PDR5 is read while PCR5 bits are set to 1, the value
stored in PDR5 are read. If PDR5 is read while PCR5 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR5.
4 to 0  All 1  Reserved
These bits are always read as 1.
9.3.4 Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 0  Reserved
These bits are always read as 0.
5 PUCR55 0 R/W Only bits for which PCR5 is cleared are valid.
The pull-up MOS of the corresponding pins enter the on-
state when this bit is set to 1, while they enter the off-
state when this bit is cleared to 0.
4 to 0  All 0  Reserved
These bits are always read as 0.