Datasheet

Rev. 3.00 Sep. 14, 2006 Page xiv of xxviii
12.5.4 Timing of Counter Clearing by Compare Match .............................................. 183
12.5.5 Buffer Operation Timing .................................................................................. 184
12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 185
12.5.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... 186
12.5.8 Timing of Status Flag Clearing......................................................................... 186
12.6 Usage Notes...................................................................................................................... 187
Section 13 Watchdog Timer..............................................................................191
13.1 Features............................................................................................................................. 191
13.2 Register Descriptions........................................................................................................ 192
13.2.1 Timer Control/Status Register WD (TCSRWD) .............................................. 192
13.2.2 Timer Counter WD (TCWD)............................................................................ 194
13.2.3 Timer Mode Register WD (TMWD) ................................................................ 194
13.3 Operation .......................................................................................................................... 195
Section 14 Serial Communication Interface 3 (SCI3).......................................197
14.1 Features............................................................................................................................. 197
14.2 Input/Output Pins.............................................................................................................. 199
14.3 Register Descriptions........................................................................................................ 199
14.3.1 Receive Shift Register (RSR) ........................................................................... 200
14.3.2 Receive Data Register (RDR)........................................................................... 200
14.3.3 Transmit Shift Register (TSR).......................................................................... 200
14.3.4 Transmit Data Register (TDR).......................................................................... 200
14.3.5 Serial Mode Register (SMR) ............................................................................ 201
14.3.6 Serial Control Register 3 (SCR3) ..................................................................... 202
14.3.7 Serial Status Register (SSR) ............................................................................. 204
14.3.8 Bit Rate Register (BRR) ................................................................................... 206
14.3.9 Sampling Mode Register (SPMR) .................................................................... 211
14.4 Operation in Asynchronous Mode.................................................................................... 212
14.4.1 Clock................................................................................................................. 212
14.4.2 SCI3 Initialization............................................................................................. 213
14.4.3 Data Transmission ............................................................................................ 214
14.4.4 Serial Data Reception ....................................................................................... 216
14.5 Operation in Clocked Synchronous Mode........................................................................ 219
14.5.1 Clock................................................................................................................. 219
14.5.2 SCI3 Initialization............................................................................................. 220
14.5.3 Serial Data Transmission.................................................................................. 220
14.5.4 Serial Data Reception (Clocked Synchronous Mode) ...................................... 223
14.5.5 Simultaneous Serial Data Transmission and Reception.................................... 225
14.6 Multiprocessor Communication Function ........................................................................ 227