Datasheet

Rev. 3.00 Sep. 14, 2006 Page xix of xxviii
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/36912 Group.................................................................3
Figure 1.2 Internal Block Diagram of H8/36902 Group.................................................................4
Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A)........................................................... 5
Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A)........................................................... 6
Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B) ..............................................7
Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) ..............................................8
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 12
Figure 2.1 Memory Map (2) ......................................................................................................... 13
Figure 2.2 CPU Registers ............................................................................................................. 14
Figure 2.3 Usage of General Registers .........................................................................................15
Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 16
Figure 2.5 General Register Data Formats (1)..............................................................................18
Figure 2.5 General Register Data Formats (2)..............................................................................19
Figure 2.6 Memory Data Formats.................................................................................................20
Figure 2.7 Instruction Formats......................................................................................................31
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 35
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 37
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 38
Figure 2.11 CPU Operation States................................................................................................ 39
Figure 2.12 State Transitions........................................................................................................ 40
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address...................................................................................................................... 41
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 56
Figure 3.2 Stack Status after Exception Handling ........................................................................ 58
Figure 3.3 Interrupt Sequence.......................................................................................................60
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 61
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 63
Figure 4.2 Address Break Interrupt Operation Example (1).........................................................67
Figure 4.2 Address Break Interrupt Operation Example (2).........................................................68