Datasheet

Section 12 Timer W
Rev. 3.00 Sep. 14, 2006 Page 188 of 408
REJ09B0105-0300
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1
T2
N H'0000
Figure 12.24 Contention between TCNT Write and Clear
TCNT
Clock before switching
N
N+1 N+2 N+3
Clock after switching
Count clock
The change in signal level at clock switching is
assumed to be a rising edge, and TCNT
increments the count.
Figure 12.25 Internal Clock Switching and TCNT Operation