Datasheet

Section 13 Watchdog Timer

Rev. 3.00 Sep. 14, 2006 Page 193 of 408

REJ09B0105-0300

Bit Bit Name

Initial

Value R/W Description

2 WDON 1 R/W Watchdog Timer On

TCWD starts counting up when the WDON bit is set to 1

and halts when the WDON bit is cleared to 0. The

watchdog timer is enabled in the initial state. When the

watchdog timer is not used, clear the WDON bit to 0.

[Setting conditions]

• Reset

• When 1 is written to the WDON bit and 0 is written to

the B2WI bit while the TCSRWE bit = 1

[Clearing conditions]

• When 0 is written to the WDON bit and 0 is written to

the B2WI bit while the TCSRWE bit = 1

1 B0WI 1 R/W Bit 0 Write Inhibit

This bit can be written to the WRST bit only when the

write value of the B0WI bit is 0. This bit is always read as

0 WRST* 0 R/W Watchdog Timer Reset

[Setting condition]

• When TCWD overflows and an internal reset signal is

generated

[Clearing conditions]

• Reset by the RES pin

• When 0 is written to the WRST bit and 0 is written to

the B0WI bit while the TCSRWE bit = 1

Note: * The WRST bit cannot be modified to 1.