Datasheet

Section 14 Serial Communication Interface 3 (SCI3)
Rev. 3.00 Sep. 14, 2006 Page 198 of 408
REJ09B0105-0300
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors
External
clock
Baud rate
generator
Transmit/receive
control circuit
BRC BRR
SMR
SCR3
SPMR
SSR
TDR
RDR
TSR
RSR
Internal clock (φ/64,φ/16, φ/4, φ)
Clock
SCK3
TXD
RXD
Interrupt request
(TEI, TXI, RXI, ERI)
Noise
filter circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
SPMR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Sampling mode register
Figure 14.1 Block Diagram of SCI3