Datasheet

Section 14 Serial Communication Interface 3 (SCI3)
Rev. 3.00 Sep. 14, 2006 Page 221 of 408
REJ09B0105-0300
Figure 14.12 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
data
Bit 1Bit 0 Bit 7 Bit 0
1 frame 1 frame
Bit 1 Bit 6
Bit 7
TDRE
TEND
LSI
operation
User
processing
TXI interrupt request generated
Data written
to TDR
TDRE flag
cleared
to 0
TXI interrupt
request
generated
TEI interrupt request
generated
Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode