Datasheet

Section 15 I
2
C Bus Interface 2 (IIC2)
Rev. 3.00 Sep. 14, 2006 Page 243 of 408
REJ09B0105-0300
Bit Bit Name Initial Value R/W Description
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
In master mode with the I
2
C bus format, when arbitration is
lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of the TRS
bit should be made between transfer frames.
After data receive has been started in slave receive mode,
when the first seven bits of the receive data agree with the
slave address that is set to SAR and the eighth bit is 1,
TRS is automatically set to 1. If an overrun error occurs in
master mode with the clock synchronous serial format,
MST is cleared to 0 and slave receive mode is entered.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3 to 0 CKS3 to
CKS0
All 0 R/W Transfer Clock Select 3 to 0
These bits should be set according to the necessary
transfer rate (see table 15.2) in master mode. In slave
mode, these bits are used reservation of the set up time in
transmit mode. The time is 10t
cyc
when CKS3 = 0, and
20t
cyc
when CKS3 = 1.