Datasheet

Section 15 I
2
C Bus Interface 2 (IIC2)
Rev. 3.00 Sep. 14, 2006 Page 246 of 408
REJ09B0105-0300
Bit Bit Name Initial Value R/W Description
3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin
outputs high. When SCLO is 0, SCL pin outputs low.
2  1  Reserved
This bit is always read as 1.
1 IICRST 0 R/W IIC Control Part Reset
This bit resets the control part except for I
2
C registers. If this
bit is set to 1 when hang-up occurs because of
communication failure during I
2
C operation, I
2
C control part
can be reset without setting ports and initializing registers.
0  1  Reserved
This bit is always read as 1.
15.3.3 I
2
C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit Bit Name Initial Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
2
C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
In master mode with the I
2
C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of the
clock for the final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait
inserted.
The setting of this bit is invalid in slave mode with the I
2
C bus
format or with the clocked synchronous serial format.
5, 4  All 1  Reserved
These bits are always read as 1.