Datasheet

Section 16 A/D Converter
Rev. 3.00 Sep. 14, 2006 Page 276 of 408
REJ09B0105-0300
Therefore, byte access to ADDR should be done by reading the upper byte first then the lower
one. ADDR is initialized to H'0000.
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel A/D Data Register to Be Stored Results of A/D Conversion
AN0 ADDRA
AN1 ADDRB
AN2 ADDRC
AN3 ADDRD
16.3.2 A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit Bit Name
Initial
Value R/W Description
7 ADF 0 R/W A/D End Flag
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all the channels
selected in scan mode
[Clearing condition]
• When 0 is written after reading ADF = 1
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled by
ADF when 1 is set
5 ADST 0 R/W A/D Start
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when conversion on
the specified channel is complete. In scan mode,
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or a transition to standby mode.