Datasheet

Section 1 Overview
Rev. 3.00 Sep. 14, 2006 Page 1 of 408
REJ09B0105-0300
Section 1 Overview
1.1 Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
 Upward-compatible with H8/300 CPU on an object level
 Sixteen 16-bit general registers
 62 basic instructions
• Various peripheral functions
 Timer B1* (8-bit timer)
 Timer V (8-bit timer)
 Timer W (16-bit timer)
 Watchdog timer
 SCI3 (Asynchronous or clocked synchronous serial communication interface)
 10-bit A/D converter
 I
2
C bus interface* (conforms to the Philips I
2
C bus interface functions)
 POR/LVD (Power-on reset and low-voltage detection circuits)
 Address break
Note: * Available for the H8/36912 Group only.
• On-chip memory
Product Classification Type ROM RAM Remarks
H8/36912F HD64F36912G 8 kbytes 1,536 bytes Flash memory
version
(F-ZTAT
TM
version)
H8/36902F HD64F36902G 8 kbytes 1,536 bytes
H8/36912 HD64336912G 8 kbytes 512 bytes
H8/36911 HD64336911G 4 kbytes 256 bytes
H8/36902 HD64336902G 8 kbytes 512 bytes
H8/36901 HD64336901G 4 kbytes 256 bytes
Masked ROM
version
H8/36900 HD64336900G 2 kbytes 256 bytes
Note: F-ZTAT
TM
is a trademark of Renesas Technology Corp.