Datasheet

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Rev. 3.00 Sep. 14, 2006 Page 294 of 408
REJ09B0105-0300
EEPROM and a transition to standby mode or subsleep mode must be made. Until this processing
is completed, the power supply voltage must be higher than the lower limit of the guaranteed
operating voltage.
When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and rises
above the Vint (U) (Typ. = 4.0 V) voltage, the LVDI circuit sets the LVDINT signal to 1. If the
LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is
simultaneously generated.
If the power supply voltage (Vcc) falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters
low voltage detection reset operation (when LVDRE = 1).
LVDINT
Vcc
Vint (D)
Vint (U)
VSS
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
LVDDE
Vreset1
Figure 17.5 Operational Timing of LVDI Circuit