Datasheet

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Rev. 3.00 Sep. 14, 2006 Page 297 of 408
REJ09B0105-0300
(4) Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits
The low-voltage detection circuit is enabled after reset. To enable or disable the low-voltage
detection circuit correctly, follow the procedure described below. Figure 17.7 shows the timing for
the operation and release of the low-voltage detection circuit.
1. To disable the low-voltage detection circuit, clear all of the LVDRE, LVDDE, and LVDUE
bits to 0. Then, clear the LVDE and BGRE bits to 0. Set the VDDII bit in LVDCR if
necessary. The LVDE and BGRE bits must not be cleared to 0 at the same timing as the
LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
2. To enable the low-voltage detection circuit, set the LVDE and BGRE bits in LVDCR to 1.
When the voltages input on the ExtU and ExtD pins are used as the compared voltage, clear
the LVDDII bit to 0.
3. Wait for 50 µs (t
LVDON
) given by a software timer until the reference voltage and the low-
voltage-detection power supply have settled. Then, clear the LVDDF and LVDUF bits in
LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, if necessary.
Longer than one instruction operation time
LVDRE
LVDDE
LVDUE
VDDII
t
LVDON
BGRE
LVDE
Figure 17.7 Timing for Enabling/Disabling of Low-Voltage Detection Circuit