Datasheet

Section 1 Overview
Rev. 3.00 Sep. 14, 2006 Page 3 of 408
REJ09B0105-0300
1.2 Internal Block Diagram
P17/IRQ3/TRGV
P14/IRQ0
P57/SCL
P56/SDA
P55/WKP5/ADTRG
PC0/OSC1
PC1/OSC2/CLKOUT
V
CL
V
SS
V
CC
RES TEST NMI
AV
CC
P22/TXD
P21/RXD
P20/SCK3
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
P76/TMOV
P75/TMCIV
P74/TMRIV
E10T_0*
E10T_1*
E10T_2*
Port 7Port 8
Port 2 Port 1Port 5
Data bus (upper)
CPU
H8/300H
Data bus (lower)
Port C
PB3/AN3/ExtU PB2/AN2/ExtD
PB1/AN1 PB0/AN0
Port B
On-chip
oscillator
(OSC1) (OSC2)
System
clock
generator
RAM
Timer W
SCI3
IIC2
Watchdog
timer
Timer V
Timer B1
A/D
converter
POR & LVD
ROM
Address bus
Note: * Can also be used for the E7 or E8 emulator.
Figure 1.1 Internal Block Diagram of H8/36912 Group