Datasheet
Section 19 List of Registers
Rev. 3.00 Sep. 14, 2006 Page 309 of 408
REJ09B0105-0300
19.3 Register States in Each Operating Mode
Register
Name
Reset
Active
Sleep
Subsleep
Standby
Module
LVDCR Initialized — — — —
LVDC
LVDSR Initialized — — — —
CKCSR Initialized — — — — Clock oscillator
RCCR Initialized — — — — On-chip oscillation
RCTRMDPR Initialized — — — —
RCTRMDR Initialized — — — —
ICCR1 Initialized — — — — IIC2
ICCR2 Initialized — — — —
ICMR Initialized — — — —
ICIER Initialized — — — —
ICSR Initialized — — — —
SAR Initialized — — — —
ICDRT Initialized — — — —
ICDRR Initialized — — — —
TMB1 Initialized — — — — Timer B1
TCB1/TLB1 Initialized — — — —
TMRW Initialized — — — — Timer W
TCRW Initialized — — — —
TIERW Initialized — — — —
TSRW Initialized — — — —
TIOR0 Initialized — — — —
TIOR1 Initialized — — — —
TCNT Initialized — — — —
GRA Initialized — — — —
GRB Initialized — — — —
GRC Initialized — — — —
GRD Initialized — — — —
FLMCR1 Initialized — — Initialized Initialized ROM
FLMCR2 Initialized — — Initialized Initialized
EBR1 Initialized — — Initialized Initialized
FENR Initialized — — Initialized Initialized
TCRV0 Initialized — — Initialized Initialized Timer V










