Datasheet

Appendix
Rev. 3.00 Sep. 14, 2006 Page 394 of 408
REJ09B0105-0300
PDR
PCR
SBY
Internal data bus
PMRC0
EXTALI
CPG
PDR:
PCR:
Portdata register
Portcontrol register
[Legend]
Figure B.16 Port C Block Diagram (PC0)
B.2 Port States in Each Operating State
Port Reset Active Sleep Subsleep Standby
P17, P14 High impedance Functioning Retained Retained High impedance*
P22 to P20 High impedance Functioning Retained Retained High impedance
P57 to P55 High impedance Functioning Retained Retained High impedance*
P76 to P74 High impedance Functioning Retained Retained High impedance
P84 to P80 High impedance Functioning Retained Retained High impedance
PB3 to PB0 High impedance High
impedance
High
impedance
Retained High impedance
PC1, PC0 High impedance Functioning Retained Retained High impedance
Note: * High level output when the pull-up MOS is in on state.