Datasheet

Rev. 3.00 Sep. 14, 2006 Page 401 of 408
REJ09B0105-0300
Item Page Revision (See Manual for Details)
Figure 2.1 Memory Map (2) 13
H8/36911
H8/36901
(Masked ROM version
(under planning))
Interrupt vector
H'0000
H'0045
H'0046
H8/36900
(Masked ROM version
(under planning))
Interrupt vector
H'0000
H'0045
H'0046
Relative Module Exception Sources
IIC2* IIC_2 transmit data empty
IIC_2 transmit end
IIC_2 receive error
Timer B1* Timer B1 overflow
Table 3.1 Exception Sources
and Vector Address
48
Note: * Available for the H8/36912 Group only.
Figure 5.1 Block Diagram of
Clock Pulse Generators
69
System
clock
oscillator
Duty
correction
circuit
OSC 1
OSC 2
φ OSC
Clock
divider
On-chip
oscillator
R OSC
R OSC
R OSC /2
R OSC /4
Bit Bit Name
Description
1
0
RCPSC1
RCPSC0
Division Ratio Select for On-chip Oscillator
The division ratio of R
OSC
changes right after
rewriting this bit.
These bits can be written to only when the CKSTA
bit in CKCSR is 0.
0X: R
OSC
(not divided)
10: R
OSC
/2
11: R
OSC
/4
5.2.1 RC Control Register
(RCCR)
71
Bit Bit Name Description
4 TRMDRWE Trimming Date Register Write Enable
This register can be written to when the LOCKDW
bit is 0 and this bit is 1.
[Setting condition]
• When writing 0 to the WRI bit while writing 1 to
the TRMDRWE bit while the PRWE bit is 1
[Clearing conditions]
• Reset
• When writing 0 to the WRI bit and writing 0 to
the TRMDRWE bit while the PRWE bit is 1
5.2.2 RC Trimming Data
Protect Register
(RCTRMDPR)
73