Datasheet

Rev. 3.00 Sep. 14, 2006 Page 402 of 408
REJ09B0105-0300
Item Page Revision (See Manual for Details)
Bit Bit Name Description
7
6
5
4
3
2
1
0
TRMD7
TRMD6
TRMD5
TRMD4
TRMD3
TRMD2
TRMD1
TRMD0
Trimming Data
In the flash memory version, the trimming
data is loaded from the flash memory to this
register right after a reset. These bits are
always read as undefined value.
As for the masked ROM version (under
planning), the on-chip oscillator frequency
can be trimmed by rewriting these bits.
5.2.3 RC Trimming Data
Register (RCTRMDR)
73
Bit Bit Name Description
7
6
PMRC1
PMRC0
Port C Function Select 1 and 0
5.2.4 Clock Control/Status
Register (CKCSR)
74
Figure 5.5 Timing Chart of
Switching On-chip Oscillator
Clock to External Clock
78
Note: * The φ halt duration is the duration from the timing when the
φ clock stops to the first
rising edge of the φ
OSC
clock after six clock cycles of the φ
RC
clock have elapsed.
Frequency (MHz) 12
R
S
(Max.) 50 Ω
Table 5.1 Crystal Resonator
Parameters
82
Section 7 ROM 97
The features of the 12-kbyte (including 4 kbytes as the E7 or E8
control program area) flash memory built into the HD64F36912G
and HD64F36902G are summarized below.
Figure 7.1 Flash Memory
Block Configuration
98 ← Programming unit: 64 kbytes →
Host Bit Rate System Clock Frequency Range of LSI
9600bps 8 MHz (on-chip oscillator clock)
4800bps 8 MHz (on-chip oscillator clock)
2400bps 8 MHz (on-chip oscillator clock)
Table 7.3 System Clock
Frequencies for which
Automatic Adjustment of LSI
Bit Rate is Possible
105
Figure 7.4 Erase/Erase-
Verify Flowchart
111
Read verify data
Ye s
No
Increment address
Verify data = all 1s ?
Section 8 RAM 115
Note: * When the E7 or E8 is used, area H'F980 to H'FD7F must
not be accessed.